Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2002-06-26
2004-06-22
Nguyen, Linh M. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C331S046000
Reexamination Certificate
active
06753711
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to frequency synthesizers, and more specifically, to a method and apparatus for reducing phase noise in synthesizers.
2. Background of the Invention
Frequency synthesizers are primarily used in radio-frequency (RF) communications equipment, but have also found general-purpose application in digital computing systems as clock synthesizers and various other applications where precise signal generation and reception are critical.
A phase-lock loop circuit typically is present at the core of a frequency synthesizer. A phase detector compares the output of the frequency synthesizer with a reference signal that may be divided down from a high-frequency clock. The output of the frequency synthesizer may also be divided down to provide a low frequency signal for phase comparison, depending on the frequency of the signal being generated by the frequency synthesizer.
Direct up-conversion or down-conversion of a high-frequency signal, while providing a simple single loop system, is typically not used in high accuracy synthesizer applications. The phase noise present at the output of the synthesizer within the bandwidth of the loop filter is a function of the phase noise of the comparison reference frequency and various noise sources present within the loop filter, phase comparator and other components of the loop. The phase noise for a single loop system directly reflects the phase noise of the reference source.
A multi-loop or “summing loop” synthesizer reduces the phase noise of the synthesizer output by providing multiple reference comparisons that result in feedback adjustment of the synthesizer output frequency (and phase). A low frequency reference having much lower phase noise is used to fine-tune the synthesizer output. However, the phase comparison itself provides a theoretical and practical limit on synthesizer output phase noise because the phase noise of the phase comparator adds a contribution to the total phase noise at the synthesizer output. Further, control of the sideband selection is complicated in a multi-loop synthesizer, as the loop can lock up at either the sum or difference frequencies of the combined signal.
Phase comparators are implemented in either digital circuitry or analog circuitry. Phase noise in an analog phase comparator is a direct function of in-loop-bandwidth noise voltages that directly affect synthesizer oscillator output. Phase noise in a digital phase comparator is caused by any number of factors such as sampling hysteresis, non-linear or chaotic input circuit behavior and digital circuit jitter internal to the phase comparator. The phase noise of a digital phase comparator is typically at least an order of magnitude greater than that of a high-quality analog phase comparator.
Digital phase comparators are desirable for use in frequency synthesizers, as they typically provide a phase-lock loop with a more accurate and higher-speed frequency acquisition than a phase-lock loop using an analog phase comparator. Digital phase comparators may also provide a more accurate quadrature (sideband) relationship than an analog phase comparator. The above-incorporated patent application discloses a hybrid phase-lock loop that switches between digital phase comparison and analog phase comparison to provide improved signal acquisition and reduced phase noise. However, the phase-lock loop disclosed therein is a single-loop system and the techniques disclosed do not apply directly to a multi-loop synthesizer, and does not provide a mechanism for preventing erroneous lock-up in a multi-loop configuration.
Therefore, it would be desirable to provide a multi-loop frequency synthesizer including a digital phase comparator and method having reduced phase noise, while maintaining high acquisition speed and accuracy.
SUMMARY OF THE INVENTION
The above objective of providing reduced phase noise and high acquisition speed and accuracy in a frequency synthesizer is achieved in a phase-lock loop circuit and method. The phase-lock loop circuit includes a digital phase comparator having a first input and a second input coupled to one of multiple external loops, a loop filter and a sweep control circuit for resolving lock ambiguities in multiple external loops by setting an initial sweep direction of the loop filter.
The apparatus may be embodied in a frequency synthesizer including a fine loop, a coarse loop and an output voltage-controlled oscillator, where the phase-lock loop circuit output is coupled to an input of the output voltage-controlled oscillator for providing the output of the frequency synthesizer.
The foregoing and other objectives, features, and advantages of the invention will be apparent from the following, more particular, description of the preferred embodiment of the invention, as illustrated in the accompanying drawings.
REFERENCES:
patent: 5210509 (1993-05-01), Greeff et al.
patent: 5838749 (1998-11-01), Casper et al.
patent: 5963608 (1999-10-01), Casper et al.
McCollum Robert L.
Taylor James W.
Comtech EF Data
Harris A. Mitchell
Moy Jeffrey D.
Nguyen Linh M.
Weiss, Moy & Harris P.C.
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