Digital still camera and image data processor

Details Digital still camera and image data processor Digital still camera and image data processor

1999-08-10

2003-05-27

Kelley, Chris (Department: 2613)

Pulse or digital communications

Bandwidth reduction or expansion

Television or motion video signal

C348S663000, C348S668000

Reexamination Certificate

active

06570925

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a digital still camera and an image data processor. More particularly, the present invention relates to a digital still camera that compresses a video signal acquired by photographing an object with a CCD imaging device, stores it in a storage element, reads said compressed video signal from the storage element and reproduces said video signal. Further, the present invention particularly relates to an image data processor wherein time required for image data expansion processing is reduced by generating luminance data and color difference data having a first data length and generating therefrom a block of data to be written composed of luminance data and color difference data having second data length equivalent to the double of the first data length, supplying these data to be written to a frame memory in units of block and writing the block of data to the frame memory.
2. Description of the Related Art
A digital still camera writes image data output from a large scale integrated circuit (LSI) for expansion to a frame memory when image data (luminance data and color difference data) compressed and stored after imaging is reproduced.
FIG. 1
shows a configuration of an image data expansion processor
200
used in the conventional digital still camera. The processor
200
is composed of an expansion processing unit (LSI for expansion)
201
for performing data expansion processing on compressed image data Vcmp which is a reproduced data from a PC card and others, a buffer memory
202
for temporarily storing an image data Vout output from the expansion processing unit
201
, a frame memory
204
Y for storing a luminance data Y of the image data Vout, a frame memory
204
C for storing a blue color difference data Cb and a red color difference data Cr of the image data Vout and a memory controller
203
for reading the image data Vout from the buffer memory
202
and sequentially writing it to the frame memories
204
Y and
204
C.
The expansion processing unit
201
outputs the luminance data Y, the blue color difference data Cb and the red color difference data Cr. They respectively have 8-bit data length and are sequentially output in units of block composed of “eight pixels×8 lines” as the image data Vout.
The luminance data Y, the blue color difference data Cb and the red color difference data Cr correspond to a video signal in “4 to 2 to 2” mode. In the case of the “4 to 2 to 2” mode, these color difference data Cb and Cr respectively include a half of the information of luminance data Y. That is, in the case of the “4 to 2 to 2” mode, these color difference data Cb and Cr are composed of “4 pixels×8 lines” shown in
FIGS. 2B and 2C
while the luminance data Y is composed of “8 pixels×8 lines” shown in FIG.
2
A.
Therefore, the expansion processing unit
201
outputs two blocks of luminance data Y, one block of blue color difference data Cb and one block of red color difference data Cr repeatedly in the above order, as shown in FIG.
3
A. In this case, the color difference data Cb and Cr are respectively composed of “8 pixels×8 lines” as one block. Therefore, they have an area corresponding to two blocks of luminance data Y. The respective pixel data b
0
, b
2
, b
4
, - - - , r
0
, r
2
, r
4
, - - - of the color difference data Cb and Cr shown in
FIGS. 2B and 2C
are data in the same position as the pixel data y
0
, y
2
, y
4
, - - - of the luminance data Y shown in FIG.
2
A.
As described above, the luminance data Y, the color difference data Cb and Cr sequentially output from the expansion processing unit
201
as image data Vout are sequentially stored in the frame memories
204
Y and
204
C under the control of the memory controller
203
as shown in
FIG. 3B
after the above data is temporarily stored in the buffer memory
202
.
If the luminance data Y is illustratively stored in the frame memory
204
Y, an address (RAS address) in the direction of lines is switched every 8 pieces of pixel data as shown in FIG.
4
and pixel data is written as to 64 pieces of pixel data, y
0
to y
63
constituting the luminance data Y
0
, Y
1
, Y
2
, Y
3
, - - - of each block. Therefore, as shown in
FIG. 3C
, time, Tad, for switching an address is required every time 8 pieces of pixel data are written. As a result, time required for writing pixel data for one block in the frame memory
204
Y is longer than the time required for outputting the pixel data y
0
to y
63
of one block from the expansion processing unit
201
.
Also, if the color difference data Cb and Cr are illustratively stored in the frame memory
204
C, an address (RAS address) in the direction of lines is switched every 8 pieces of pixel data as shown in FIG.
5
and pixel data are written as to 64 pieces of pixel data constituting the color difference data Cb
0
, Cr
0
, Cb
2
, Cr
2
, - - - of each block. In this case, the blue color difference data Cb
0
, Cb
2
, - - - are written to the even addresses of each line as “b0, b2, b4, b6, b0, b2, b4, b6”, “b8, b10, b12, b14, b8, b10, b12, b14”, - - - and the red color difference data Cr
0
, Cr
2
, - - - are written to the odd addresses of each line as “r0, r2, r4, r6, r0, r2, r4, r6”, “r8, r10, r12, r14, r8, 10, r12, r14”, - - - .
As described above, if the color difference data Cb and Cr are stored in the frame memory
204
C, the time, Tad, for switching an address is also required every time 8 pieces of pixel data are written. As a result, time required for writing one block of pixel data to the frame memory
204
C is longer than time required for outputting one block of pixel data from the expansion processing unit
201
.
In the conventional digital still camera, to adjust difference between time required for writing the above one block of pixel data to the frame memories
204
Y and
204
C and time required for outputting one block of pixel data from the expansion processing unit
201
, the processing of the expansion processing unit
201
stops every time the image data Vout of one block is output (see a period Tst in which expansion processing is stopped shown in
FIG. 3A
) and, at the next block, the pixel data is written to the frame memories
204
Y and
204
C at the same timing as the output timing of the expansion processing unit
201
has been executed.
Similarly, in the conventional image data processor
200
, writing image data, Vout, to the frame memories
204
Y and
204
C takes much time and to adjust time, a measure of stopping the processing of the expansion processing unit
201
has been taken. Therefore, there has been a problem that it takes relatively much time to execute processing for expanding image data.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a digital still camera and an image data processor wherein time required for expanding image data is reduced.
In carrying out the present invention as one preferred embodiment, I provide a digital still camera that compresses a video signal acquired by photographing an object with a CCD imaging device, stores it in a storage element, reads said compressed video signal from the storage element and reproduces said video signal. The digital still camera comprises expansion processing means for performing expansion processing on said compressed video signal and outputting the video signal in units of block as luminance data and color difference data respectively having a first data length, a frame memory having a second data length equivalent to the double of the first data length, video data block generating means for generating a block of video data having the second data length by connecting the luminance data and the color difference data respectively having the first data length and output from the expansion processing means in units of block, and writing means for writing a signal output from the video data block generating means to the frame memory in units of block of said video data.
Further, as another preferred embodiment, I provide an image data pr

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