Digital step generators and circuits, systems and methods using

Details Digital step generators and circuits, systems and methods using Digital step generators and circuits, systems and methods using

1996-12-03

1999-01-19

Tran, Toan

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Generating staircase output

327334, 327530, H03K 402

Patent

active

058617671

ABSTRACT:
A step generator 800 including at least one gate 805 and a voltage divider 806 coupled to an output of gate 805. The selected node of voltage divider 806 provides an output V.sub.OUT of generator 800. Circuitry 801 presents a signal to an input of gate 805 to initiate current flow through voltage divider 806.

REFERENCES:
patent: 4168498 (1979-09-01), Kubota et al.
patent: 4446436 (1984-05-01), Ireland
patent: 4855628 (1989-08-01), Jun
patent: 4864162 (1989-09-01), Maoz
patent: 5130577 (1992-07-01), Neidorff et al.
patent: 5196732 (1993-03-01), Takahashi et al.
patent: 5546042 (1996-08-01), Tedrow et al.
"A 64-K dynamic RAM needs only one 5-volt supply to outstrip 16-K parts" by G.R. Mohan Rao and John Hewkin, Electronics, Sep. 28, 1978 pp. 109-116.
"A 1Mb CMOS DRAM with Design-for-Test Functions" by Neal, Holland, Inoue, Loh, mcAdams,& Potett, ISSC Conv. 1986, Digest of Tech. Papers. pp. 264-265.
"A 4Mb DRAM with Half Internal-Voltage Bitlines Precharge", ISSC Conf. 1986, Digest of Tech. Papers, pp. 270-271.
"High-Speed Sensing Scheme for CMOS DRAM's" by Dhong et al., in the IEEE Journal of Solid State Circuit, vol. 23, No. 1, Feb. 1988.
"A 50-ns 16 Mb DRAM with a 10-ns Data Rate and On-Chip ECC" by Kalter et al. IEEE Journal of Solid State Circuits, vol.25, No. 5 in Oct. 1990.
"A Variable Precharge Voltage Sensing" by Kirihara et al. IEE Journal of Solid State Circuits, vol. 30, No. 1, in Jan., 1995.
"Cross-Coupled Charge-Transfer Sense Amplifier and Latch Sense Scheme or High-Density FET Memories" by Gray, in IBM J.Res. Develop., vol. 24, No. 3, May 1980.
"A 5V-only 64K Dynamic RAM" by White et al. in IEEE International Solid-State Circuits Conference, 1980, Friday, Feb. 15, 1980, pp. 230-231.
"Offset-Trimming Bit-Line Sensing Scheme for Gigabit-Scale DRAM's" by Suh et al. in the IEEE Journal of Solid-State Circuits, vol. 31, No. 7, Jul. 1996, pp. 1025-1028.
"A Full Bit Prefetch Architecture for Synchronous DRAM's" by Sunaga et al., IEEE Journal of Solid-State Circuits, vol. 30, No. 9, Sept. 1995, pp. 998-1005.
"DRAM Macros for ASIC Chips" by Sunaga et al., IEEE Journal of Solid State Circuits, vol. 30, No. 9, Sep. 1995 pp. 1006-1014.

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