Digital signal reproducing circuit

Dynamic information storage or retrieval – Binary pulse train information signal – Binary signal gain processing

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Details

360 51, G11B 576, G11B 509

Patent

active

047138025

ABSTRACT:
A digital signal reproducing circuit for correcting phase errors of digital signals, and for synchronizing a bit synchronizing clock to the digital signal, including at least a PLL circuit connected to a wave-shaping circuit, a pattern detector connected to the PLL circuit for detecting the specified signal patterns of the digital signal, and a circuit for detecting the phase errors of the inputted digital signals and correcting properly the digital signals after the specified signal pattern are detected by the pattern detector.

REFERENCES:
patent: 4495474 (1985-01-01), Nishikawa et al.
patent: 4504960 (1985-03-01), Yamada
patent: 4583211 (1986-04-01), Nishikawa et al.

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