Digital signal receiving circuit

Pulse or digital communications – Receivers – Automatic baseline or threshold adjustment

Reexamination Certificate

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Details

C375S354000, C375S340000, C329S321000, C329S350000, C329S349000, C327S058000, C327S072000, C327S052000, C327S064000, C327S060000, C327S061000, C327S062000, C327S090000

Reexamination Certificate

active

07570715

ABSTRACT:
A delayed peak detector detects a peak level of an input signal IN at timing lagged behind a peak detector, and a peak difference detector detects a peak difference PLD between a delayed peak level DPL and a peak level PL. A reset portion outputs a reset signal BRS for a bottom detector when a level difference between the peak level PL and a bottom level BL exceeds a predetermined value comparable with the amplitude of the input signal IN and the peak difference PLD exceeds an allowable peak difference PLM. It is thus possible to replace the bottom level BL outputted from the bottom detector with a bottom level based on a latest input signal IN.

REFERENCES:
patent: 5025176 (1991-06-01), Takeno
patent: 5412692 (1995-05-01), Uchida
patent: 5892609 (1999-04-01), Saruwatari
patent: 6041084 (2000-03-01), Nagaraj
patent: 6292058 (2001-09-01), Ide et al.
patent: 2003/0198302 (2003-10-01), Song
patent: 10-084231 (1998-03-01), None
patent: 2001-036470 (2001-02-01), None

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