Digital signal receiver capable of receiving data encrypted and

Cryptography – Particular algorithmic function encoding – Nbs/des algorithm

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380 20, 380 49, 380 59, 380 9, H04L 908, H04L 900

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active

057844623

ABSTRACT:
In a decoding processing circuit of a digital signal receiver, a first comparison circuit detects that a prefix of packet data is inputted in a shift register on the basis of a count value of a counter circuit. In response to the result of detection, a pseudo-random binary sequence generation circuit outputs a pseudo-random binary sequence on the basis of a data group number and a data packet number outputted from the shift register and key data previously extracted by a key data fetch circuit. When a second comparison circuit detects that block data in the data packet is inputted in the shift register, an exclusive OR circuit exclusively ORs the pseudo-random binary sequence with receive data, so that decoded data is inputted in the shift register.

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