Digital signal processor with parallel multipliers

Details Digital signal processor with parallel multipliers Digital signal processor with parallel multipliers

1986-10-21

1988-09-13

Zache, Raulfe B.

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G06F 752

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047713798

ABSTRACT:
An arithmetic operation portion 3 comprises a plurality of multipliers 311 and 312 connected directly with a memory portion 1 so that multiplication processing can be performed in parallel. As a result, the processing capacity for multiplication and addition can be increased and the throughput rate of data can be improved.

REFERENCES:
patent: 4593378 (1986-06-01), McWhirter et al.
"A Single-Chip Digital Signal Processor for Voiceband Applications", Yuichi Kawakami et al., 1980 IEEE International Solid-State Circuits Conference, pp. 40-41.
Larson, "High-Speed Multiply Using Four Input Carry-Save Adder" IBM Technical Disclosure Bulletin, vol. 16, No. 7 (Dec., 1973):2053-2054.

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