Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2000-02-26
2003-04-29
Ngo, Chuong Dinh (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S603000
Reexamination Certificate
active
06557022
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
This invention relates to digital signal processors, and has particular relation to multiply-accumulate (MAC) units.
2. Background Art
Digital Signal Processors (DSPs) are specialized types of microprocessors that are specifically tailored to execute mathematical computations very rapidly. DSPs can be found in a variety of applications including compact disk players, PC disk drives, telecommunication modem banks, and cellular telephones.
In the cellular telephone context, the demand for DSP computation capability continues to grow, driven by the increasing needs of applications such as GPS position location, voice recognition, low-bit rate speech and audio coding, image and video processing, and 3G cellular modem processing. To meet these processing demands, there is a need for improved digital signal processor architectures that can process computations more efficiently.
Considerable work has been done in these areas. Applicant Sih is also an applicant in the following applications for U.S. patents:
“Multiple Bus Architecture in a Digital Signal Processor”, Ser. No. 09/044,087, filed Mar. 18, 1998, now abandoned;
“Digital Signal Processor Having Multiple Access Register”, Ser. No. 09/044,088, filed Mar. 18, 1998, now U.S. Pat. No. 6,496,920;
“Memory Efficient Instruction Storage”, Ser. No. 09/044,089, filed Mar. 18, 1998, now abandoned;
“Highly Parallel Variable Length Instructions for Controlling a Digital Signal Processor”, Ser. No. 09/044,104, filed Mar. 18, 1998, now abandoned;
“Variable Length Instruction Decoder”, Ser. No. 09/044,086, filed Mar. 18, 1998, now U.S. Pat. No. 6,425,070; and
“Digital Signal Processor with Shiftable Multiply Accumulate Unit”, Ser. No. 09/044,108, filed Mar. 18, 1998, now abandoned.
The disclosure of these applications is incorporated herein by reference.
In many signal processing algorithms, the computation (B*C)+/−(D*E) is prominent, where B, C, D, and E are 16-bit integers. This computation is invoked when performing single-pole IIR filtering, computing magnitude of a complex quantity, dot-product or cross product of 2 vectors, and interpolation. It is also used in extended-precision operations (e.g. a 32×32 multiply). Since this operation is so ubiquitous, it is desirable to have a digital signal processor complete this operation in one cycle.
Although DSPs with two multiply-accumulate (MAC) units are available (e.g. Lucent DSP16000, TI C6x), they cannot compute the desired quantity in one cycle because their MAC units are separate. If we let R
1
, R
2
, R
3
, and R
4
be general purpose 16-bit registers containing B, C, D, and E respectively, and let L
1
, L
2
, and L
3
be 40-bit result registers, then a single invocation of the computation
(
B*C
)+(
D*E
)
could be written in pseudocode on these existing processors as:
L
1
=
R
1
*
R
2
,
L
2
=
R
3
*
R
4
;
L
3
=
L
1
+
L
2
;
It should be noted that this computation takes 2 cycles on these processors.
FIG. 1
is a block diagram of a conventional MAC unit (
100
). A register file (
102
) has an input port PI
1
, and has three output ports, PO
1
, PO
2
, and PO
3
. The register file is connected to a memory (
104
). The output ports PO
2
and PO
3
are applied to a multiplier (
106
), which multiplies the signals together and applies them to one input of an adder (
108
). The adder receives its other input from PO
1
of the register file. The sum is fed back to PI
1
of the register file.
In the first clock cycle, nothing is applied to PO
1
, and R
1
and R
2
are applied to ports PO
2
and PO
3
, respectively. The product, L
1
, is fed back to the register file and placed in a temporary register attached to PO
1
. In the second clock cycle, R
3
and R
4
are applied to ports PO
2
and PO
3
, respectively, and emerge from the multiplier as L
2
. The adder combines L
2
from the multiplier with L
1
from PO
1
, produces L
3
, and feeds it back to the register bank via PI
1
. Once L
3
is in the register bank, it can be made available to the memory.
40-bit adder, and a 17×17 bit multiplier, are shown. This is conventional, but any convenient number of bits may be used
BRIEF DISCLOSURE OF THE INVENTION
Two multiply-accumulate units are coupled together so that the computation (B*C)+(D*E) can be completed in one cycle. An adder adds together the products of the two multipliers. The sum is applied to the first accumulator. Preferably, the second product is also applied to the second accumulator, and a multiplexer applies either a zero or the second product to the adder. If two unrelated computations are to be executed simultaneously, then the zero is applied, and the output of the second accumulator is fed back to the register file. If a single (B*C)+(D*E) computation is to be executed, then the second product is applied to the adder, and the output of the second accumulator is disregarded.
REFERENCES:
patent: 4771379 (1988-09-01), Ando et al.
patent: 4996661 (1991-02-01), Cox et al.
patent: 5483352 (1996-01-01), Fukuyama et al.
patent: 5764943 (1998-06-01), Wechsler
patent: 5933797 (1999-08-01), Haakansson et al.
patent: 5941940 (1999-08-01), Prasad et al.
patent: 5966652 (1999-10-01), Coad et al.
patent: 5991785 (1999-11-01), Alidina et al.
patent: 0458563 (1991-11-01), None
patent: 8301415 (1983-04-01), None
patent: 9856159 (1998-12-01), None
patent: 0122680 (2001-03-01), None
patent: 0154380 (2001-07-01), None
Fujioka, et al., “240MOPS Reconfigurable Parallel VLSI Processor for Robot Control”, IEEE, Sep. 11, 1992, pp. 1385-1390.
Chen Xufeng
Hsu De D.
Sih Gilbert C.
Brown Charles D.
Ngo Chuong Dinh
Qualcomm Incorporated
Seo Howard H.
Wadsworth Philip R.
LandOfFree
Digital signal processor with coupled multiply-accumulate units does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Digital signal processor with coupled multiply-accumulate units, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Digital signal processor with coupled multiply-accumulate units will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3066071