Boots – shoes – and leggings
Patent
1988-02-29
1989-03-07
Chan, Eddie P.
Boots, shoes, and leggings
377 64, 364900, G06F 738
Patent
active
048112674
ABSTRACT:
A digital signal processor includes a digital memory, a controller, an arithmetic operation unit and an interconnecting bus. The memory includes a shift register having an addressable output for storing values which are supplied to a multiplier circuit of the arithmetic operation unit. Use of the shift register provides a data delay minimizing the number of instructions required to implement delay processing. In the arithmetic operation unit, the output from the multiplier is connected to an arithmetic logic unit which, in turn, is connected to an accumulator. The accumulator temporarily stores data from the arithmetic logic unit and output the result onto the data bus. The operations of the signal process are directed by the controller which includes a program memory, an instruction register, and an instruction decoder.
REFERENCES:
patent: 4468786 (1984-08-01), Davis
patent: 4491910 (1985-01-01), Caudel et al.
patent: 4533992 (1985-08-01), Magar et al.
patent: 4612625 (1986-09-01), Bertrand
patent: 4617676 (1986-10-01), Jayant et al.
IBM Tech. Discl. Bull. vol. 18, No. 10, Mar. 1976, "Shift Register Implemented by Indexing a Random-Access Memory" by Esteban.
Ando Hideki
Kondo Harufusa
Machida Hirohisa
Chan Eddie P.
Mitsubishi Denki & Kabushiki Kaisha
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