Digital signal processor optimized for decoding a signal encoded

Details Digital signal processor optimized for decoding a signal encoded Digital signal processor optimized for decoding a signal encoded

1995-11-16

1997-05-27

Bocure, Tesfaldet

Pulse or digital communications

Receivers

Particular pulse demodulator or detector

371 43, H03D 100, H04L 2706

Patent

active

056338970

ABSTRACT:
An improved DSP has two internal data buses with two MAC units each receiving data from its respective data bus. A shifter is interposed between the multiply unit and the ALU and accumulate unit. The improved DSP also has a multiplexer interposed between one of the MAC units and the two data buses. The improved DSP is optimized to decode a received digital signal encoded in accordance with the Viterbi algorithm, wherein the DSP calculates a first pair of binary signals C.sub.2n and C.sub.2n+1 a Viterbi butterfly based upon a second pair of binary C.sub.n and C.sub.n+m/2, and a transitional signal a, in accordance with: C.sub.2n =minimum (C.sub.n +a, C.sub.n+m/2 -a); C.sub.2n+1 =minimum (C.sub.n -a, C.sub.n+m/2 +a).

REFERENCES:
patent: 5291524 (1994-03-01), Itakura et al.
patent: 5349608 (1994-09-01), Graham et al.
patent: 5410556 (1995-04-01), Yeh et al.
patent: 5461644 (1995-10-01), Bergmans et al.

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