Digital signal processor including address generation by execute

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395166, 3642581, 3642582, 364259, 3642613, 364DIG1, G06F 900

Patent

active

054505534

ABSTRACT:
Disclosed is a digital signal processor for processing input digital signals, comprising an address generation unit for generating an address of an addressing mode which is used for processing the input digital signals; a setting unit for setting an initial value necessary for generating the address in advance in the address generation unit; and an instruction designating unit for designating only execution and stop of address generation to the address generation unit, wherein the address generation unit in which is set the initial value is so constructed as to perform execution and stop of address generation only by designation of the execution and stop outputted from the instruction designating means.

REFERENCES:
patent: 4849921 (1989-07-01), Yasumoto et al.
patent: 4882683 (1989-11-01), Rupp et al.
patent: 5175625 (1992-12-01), Miles
patent: 5206940 (1993-04-01), Murakami et al.
IEEE International Solid-State Circuits Conference, Feb. 19, 1986, Akira Kanuma et al., "Sensors and Interface Electronics", Session IX, pp. 102-103.
IEEE International Solid-State Circuits Conference, Feb. 16, 1989, Shin--ichi Nakagawa et al, "Digital Video & Image Processing", Session 12, pp. 168-169.

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