Digital signal processor having reduced bus pre-charging operati

Details Digital signal processor having reduced bus pre-charging operati Digital signal processor having reduced bus pre-charging operati

1993-03-15

1994-12-20

Malzahn, David H.

Boots, shoes, and leggings

364707, G06F 1531

Patent

active

053750772

ABSTRACT:
A digital signal processor according to the present invention comprises a data bus, a control line for supplying a pre-charge signal at the beginning of each cycle, a first memory for providing a first data stored in a first address to the data bus at a first cycle, for receiving the first data from the data bus and storing the first data in a second address at a second cycle successively with the first cycle, a second memory for storing a second a data, an arithmetic circuit coupled to the data bus and the second memory, for receiving the first and second data at the first cycle, for performing arithmetic operation and producing a result data in response to the first data and second data at the second cycle, a pre-charge circuit for providing a potential to the data bus in response to the pre-charge signal, a pre-charge control circuit for transferring the pre-charge signal to the pre-charge circuit at the first cycle, and for inhibiting the transfer of the pre-charge signal at the second cycle. It is possible to provide a digital signal processor capable of operating at low power consumption with high integration.

REFERENCES:
patent: 5010510 (1991-04-01), Nishimura et al.
patent: 5128890 (1992-07-01), Girardeau, Jr.
patent: 5170369 (1992-12-01), Rossum
patent: 5189634 (1993-02-01), Eberle et al.
patent: 5241492 (1993-08-01), Girardeau, Jr.

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