Digital signal processor for wireless baseband processing

Details Digital signal processor for wireless baseband processing Digital signal processor for wireless baseband processing

2006-02-28

2006-02-28

Coleman, Eric (Department: 2183)

Electrical computers and digital processing systems: processing

Processing architecture

Microprocessor or multichip or multimodule processor having...

C712S010000

Reexamination Certificate

active

07007155

ABSTRACT:
A circuit employing an array of reconfigurable processing elements for wireless baseband processing. The circuit includes a first linear array of reconfigurable processing elements for processing signals from a first channel, and a second linear array of reconfigurable processing elements, coupled in parallel with the first linear array of reconfigurable processing elements, for processing signals from a second channel that is concurrent with the first channel. The circuit also includes a frame buffer array having a number of frame buffers that corresponds to a number of reconfigurable processing elements in the first and second linear arrays of processing elements. A point-to-point data bus is connected between each reconfigurable processor and an associated frame buffer. A shared data bus is connected between the first and second linear arrays of reconfigurable processing elements and the frame buffer array.

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