Digital signal processor for executing multiple instruction word

Details Digital signal processor for executing multiple instruction word Digital signal processor for executing multiple instruction word

1996-11-04

1998-10-20

Ellis, Richard L.

395562, G06F 1578

Patent

active

058261001

ABSTRACT:
A digital signal processor (10) includes a primary data bus (12), a primary instruction bus (14), a program control unit (16), an arithmetic unit (18), and a multiplier (20). Within the program control unit (16), multi-instruction words are issued from program memory (22) to the primary instruction bus (14). These multi-instruction words allow both logical and arithmetic instructions to be performed simultaneously. The arithmetic unit (18) includes a secondary data bus (44) which couples the arithmetic unit to the accumulator (34). The arithmetic unit (18) also includes a barrel shifter (48) having sign extension to reduce the number of operations required to shift data. The arithmetic logic unit (32) further includes complex arithmetic functions resulting in fewer operations per instruction and a multiplier (50) which is used for filtering operations in digital filtering and by the arithmetic unit (18).

REFERENCES:
patent: 4713748 (1987-12-01), Magar et al.
patent: 5128890 (1992-07-01), Girardeau, Jr.
patent: 5276819 (1994-01-01), Rau et al.
patent: 5506798 (1996-04-01), Shimada et al.
Texas Instruments, TMS32010 User'Guide, Digital Signal Processor Products, 1983, pp. 2-2 to 2-3, 2-6, 3-5 to 3-7, 3-10 3-14, 3-25, 3-31, 3-39 to 3-41, 3-43, and 3-60.

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