Digital signal processor evaluation chip and debug method

Details Digital signal processor evaluation chip and debug method Digital signal processor evaluation chip and debug method

1994-08-29

1996-09-17

Teska, Kevin J.

Boots, shoes, and leggings

3951831, 3642328, 3642656, 36426791, G06F 1125

Patent

active

055577628

ABSTRACT:
A digital signal processor evaluation chip has a sequencer for fetching and decoding instructions, and a processor core for executing the instructions. When the sequencer attempts to fetch an instruction from a preset break address, a register transfer instruction is supplied in place of the program instruction at that address, then clock input to the sequencer is halted. After the processor core has executed the register transfer instruction, clock input to the processor means is also halted, leaving the data transferred by the register transfer instruction available to be read.

REFERENCES:
patent: 4275441 (1981-06-01), Takeuchi
patent: 4290133 (1981-09-01), Stewart et al.
patent: 4670838 (1987-06-01), Kawata

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