Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
1999-02-24
2001-11-13
Maung, Zarni (Department: 2154)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
C712S002000, C712S010000, C711S147000
Reexamination Certificate
active
06317819
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to digital data processors and, in particular, to digital data processors that are implemented as integrated circuits to process input data in parallel, as well as to techniques for programming such data processors.
BACKGROUND OF THE INVENTION
Digital signal processor (DSP) devices are well known in the art. Such devices are typically used to process data in real time, and can be found in communications devices, image processors, video processors, and pattern recognition processors.
One drawback to many conventional DSPs is their lack of parallelization, that is, an ability to apply multiple processors in parallel to the execution of desired operations on a given data set. As can be appreciated, the parallel execution of a plurality processors can yield significant increases in processing speed, so long as the multiple processors are properly controlled and synchronized.
OBJECTS AND ADVANTAGES OF THE INVENTION
It is a first object and advantage of this invention to provide an improved DSP having a capability to enable a single instruction unit to simultaneously control a plurality of processors in parallel using a group of bits.
It is a further object and advantage of this invention to provide a technique for programming the improved DSP.
SUMMARY OF THE INVENTION
The foregoing and other problems are overcome and the objects and advantages are realized by methods and apparatus in accordance with embodiments of this invention.
In one aspect this invention teaches a digital data processor integrated circuit that includes a plurality of functionally identical first processor elements and a second processor element. The plurality of functionally identical first processor elements are bidirectionally coupled to a first cache via a crossbar switch matrix. The second processor element is coupled to a second cache. Each of the first cache and the second cache comprise a two-way, set-associative cache memory that uses a least-recently-used (LRU) replacement algorithm and that operates with a use-as-fill mode to minimize a number of wait states said processor elements need experience before continuing execution after a cache-miss.
An operation of each of the plurality of first processor elements and an operation of the second processor element are locked together during an execution of a single instruction word read from the second cache. The single instruction word specifies, in a first portion that is coupled in common to each of the plurality of first processor elements, the operation of each of the plurality of first processor elements in parallel. A second portion of the single instruction specifies the operation of the second processor element.
The digital data processor integrated circuit further includes a motion estimator having inputs coupled to an output of each of the plurality of first processor elements, and an internal data bus coupling together a first parallel port, a second parallel port, a third parallel port, an external memory interface, and a data input/output of the first cache and the second cache.
REFERENCES:
patent: 4622632 (1986-11-01), Tanimoto et al.
patent: 4641350 (1987-02-01), Bunn
patent: 4807115 (1989-02-01), Torng
patent: 4845610 (1989-07-01), Parvin
patent: 4992933 (1991-02-01), Taylor
patent: 5203002 (1993-04-01), Wetzel
patent: 5313551 (1994-05-01), Labrousse et al.
patent: 5353426 (1994-10-01), Patel et al.
patent: 5465373 (1995-11-01), Kahle et al.
patent: 5504931 (1996-04-01), Furtek
patent: 5522083 (1996-05-01), Gove et al.
patent: 5555428 (1996-09-01), Radigan et al.
patent: 5574939 (1996-11-01), Keckler et al.
patent: 5655133 (1997-08-01), Dupree et al.
patent: 5680597 (1997-10-01), Kumar et al.
patent: 5682491 (1997-10-01), Pechanek et al.
patent: 5692210 (1997-11-01), Mita et al.
patent: 5727229 (1998-03-01), Kan et al.
patent: 5752068 (1998-05-01), Gilbert
patent: 5761726 (1998-06-01), Guttag et al.
patent: 5765037 (1998-06-01), Morrison et al.
patent: 5778244 (1998-07-01), Putnins et al.
patent: 5892926 (1999-06-01), Cloutier
patent: 6038647 (2000-03-01), Shimizu
Lin Wen-Tai
Maung Zarni
LandOfFree
Digital signal processor containing scalar processor and a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Digital signal processor containing scalar processor and a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Digital signal processor containing scalar processor and a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2588662