Dynamic information storage or retrieval – Binary pulse train information signal – Binary signal gain processing
Reexamination Certificate
1998-11-03
2001-01-30
Huber, Paul W. (Department: 2753)
Dynamic information storage or retrieval
Binary pulse train information signal
Binary signal gain processing
C369S047360
Reexamination Certificate
active
06181660
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to digital signal processing circuitry and, more particularly, to digital signal processor circuits for detecting a specific pattern or patterns including synchronization (sync) signals as contained for successive transmission in digitized 1-bit serial data read out of recording media, and for performing data demodulation with respect to digital data being transferred in succession after a sync pattern to thereby reconstruct or reproduce the original digital data.
Conventionally, digital signal processor circuits of this type include an information playback system adaptable for use in reproducing information signals pre-recorded on an optical storage medium, typically, a disk-shaped optical record carrier body known as “compact disc (CD).” One typical CD record/playback architecture has been disclosed in, for example, “CD—from Audio to PCs” by Kenji Hayashi under the supervision of Fujio Mari, Corona Publishing Co., Ltd., at pp. 13-15 and 62-63. A digital signal processor as taught thereby is designed so that for a stream of digital data bits arrayed in a time sequential manner for recording on disks, a group of data in units of “clusters” of 8 bits may be used to constitute a single frame, and wherein after completion of error correction code addition and inter-frame interleaving as well as sub-code addition, a specific modulation technique, known as the “Eight-to-Fourteen Modulation (EFM),” is employed to modulate the resulting data in units of 8-bit clusters into data with 14 bits being used as a unit to thereby add thereto a margin of 3 bits. A pattern corresponding to a synchronization signal in units of frames, each of which is made up of a plurality of data items with a cluster of 17 bits added with margin bits being as a unit; thereafter, the resultant data is recorded as one (1)-bit serial data on an associative disk in the form of recording marks called the “pits.”
During reproduction of data recorded on an optical disk, a disk playback signal that is read by a pickup module from the disk is transferred via a phase locked loop (PLL) circuit as data of 1-bit serial form having a train of bits “0s” and “1s” synchronously with bit clocks. Then, serial-to-parallel conversion processing is applied to this serial data stream to thereby detect one or several sync patterns that are contained in the read data stream. The serial data stream after detection of the sync pattern(s) is converted into a 14-bit parallel data stream, which is then subject to demodulation processing thereby obtaining the demodulated, original data in units of 8-bit segments, which will be written into an associative random-access memory (RAM). Thereafter, control a read/write operation of the RAM to execute error correction through decoding of error codes and de-interleaving processing so that the original time-sequential data may be reproduced.
SUMMARY OF THE INVENTION
To obtain the intended demodulation data through detection of more than one sync signal, the aforementioned prior known demodulation/playback architecture does require the use of a shift register for use in performing serial-to-parallel conversion, a decoder used for decoding the sync pattern, demodulator means for demodulation processing, a data latch temporarily latching therein the data demodulated, a timing generator generating a latch timing signal for use with the demodulated data, and memory control means for performing write/read controls of demodulated data to/from an associated memory.
In recent years, large-capacity data storage devices for use with currently available high-density recording media in digital computer equipment—such as, for example, compact-disc read-only memory (CD-ROM) drive modules and digital versatile disk (DVD) drive units—are endlessly demanded to achieve higher playback data transfer rate. As the data transfer rate increases, semiconductor chips used for digital signal processing necessary for playback of information recorded on such CD-ROMs and DVDs tend to increase in power consumption due to an increase in operating clock frequency thereof.
In order to suppress such increase of unwanted power dissipation in semiconductor chip packages while simultaneously attaining high data transfer rates required, a prior art approach is that as shown in
FIG. 2
for example, a 2-bit shift register is used for serial-to-parallel conversion with respect to bit data read out of an optical disk which is in the 1-bit serial form along with bit clocks having a period “f” (where f is a positive number) as synchronized with the data thereby transferring the resulting converted 2-bit read data synchronously with a respective one of the rising and falling edges of read clocks of period (2×f) of the bit clocks; then, such 2-bit read data is subject to sync pattern detection and data demodulation. In this case it is possible to achieve 2-bit data transmission per (2×f)-period read clock. This in turn makes it possible to reduce power dissipation in semiconductor chips accommodating thereon the circuitry for demodulation processing while at the same time maintaining the data transfer rates required.
Unfortunately, the prior art approach is encountered with a problem as follows: when an attempt is made to use the prior art technique for sync pattern detection and data demodulation with respect to transmission of the 2-bit serial data synchronized to those read clocks having the period of (2×f), it must remain unknown which one of the bits of 2-bit data segments carries for transmission the top bit of a sync pattern as contained in a playback signal from a disk for example, which would result in an inability to determine that decoding is to be done from which bit to which bit thereby making it impossible to detect the intended sync pattern or patterns. If this is the case, lack of sync pattern detectability makes data demodulation impossible, or at least extremely difficult. Even where a sync pattern could be detected at a time, it will not be able to guarantee that the top bit of its next succeeding sync pattern is transferred from an expected read data bit that is the same as the previous one; rather, in most cases, such will be sent from different read data bits. In this case also, the intended sync pattern detection will no longer be achievable during the process of data transmission, which results in incapability to obtain any correctly demodulated data.
It is therefore an object of the present invention to provide a digital signal processing circuit for use with those which are designed to transfer n-bit read data obtainable after serial-to-parallel conversion of bit data of 1-bit serial form into n-bit read data synchronously with read clocks of period (f×n) as obtained by n frequency-division of bit clocks of period f, the digital signal processor circuit being capable of correctly detecting a specific pattern such as a synchronization pattern being contained for transmission in such n-bit read data while enabling acquisition of correct demodulation data.
It is another object of the invention to provide a digital signal processor circuit mounted in a semiconductor chip package capable of reducing operating clock frequencies and power dissipation while retaining the data transfer rate required.
To attain the foregoing objects, in accordance with one aspect of the present invention, a digital signal processing circuit is provided which at least includes—as measures for correctly detecting more than one synchronization pattern that is contained for transmission in n-bit read data to be transferred synchronously with read clocks having the period of (f×n) while obtaining correct demodulation data—a specified number, n, of shift registers for use in performing data shifting with respect to each of n-bit read data items, n decoders decoding one or several sync patterns from a stream of bits of the shift registers, a determination circuit judging and determining sync pattern detection based on the condition of detection availabl
Gunji Hiroyuki
Hirayama Hiroshi
Takeuchi Toshifumi
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Huber Paul W.
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