Digital signal processor architecture with plural multiply/accum

Details Digital signal processor architecture with plural multiply/accum Digital signal processor architecture with plural multiply/accum

1991-01-22

1992-12-29

Mai, Tan V.

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36472801, G06F 738

Patent

active

051757028

ABSTRACT:
An improved digital signal processor (DSP) architecture includes several multiply/accumulate devices (M-Unit 0-K) connected to the DSP bus through a delay line and elements for simultaneously operating the multiply/accumulate devices and a device for selectively storing accumulated values into a pre-assigned Dual-Port Randomly Accessible Memory area.

REFERENCES:
patent: 4490807 (1984-12-01), Chevillat et al.
patent: 4694416 (1987-09-01), Wheeler et al.
patent: 4896285 (1990-01-01), Ishikawa et al.
Patent Abstracts of Japan, vol. 12, No. 161 (p-702), May 17, 1988; & JP-A-62 274 426 (Daikin Ind. Ltd) Nov. 28, 1987.
1986 IEEE International Symposium on Circuits and Systems, San Jose, Calif., May 5-7, 1986, vol. 1, pp. 231-234, IEEE, New York; L. Schirm: "GOPS-A 45MHz Continuous Digital Signal Processor".

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