Digital signal processor architecture with an ALU and a serial p

Details Digital signal processor architecture with an ALU and a serial p Digital signal processor architecture with an ALU and a serial p

1987-07-02

1990-05-15

Zache, Raulfe B.

Boots, shoes, and leggings

3642401, 3642214, 364228, 364232, 36423293, 3642446, 364258, 364263, 364736, G06F 1531, G06F 1516

Patent

active

049263552

ABSTRACT:
A digital signal processor (DSP) for conducting arithmetically complex functions, is provided. The DSP is preferably embodied as a single integrated circuit chip and generally includes a microinstruction sequencer (MIS) section, an arithmetic logic unit (ALU), a serial arithmetic processor section, a RAM section, and a system data bus. The MIS includes a coded ROM, a circuit for addressing the ROM, a ROM decoder for decoding the ROM code into control and data signals, and circuitry for sending the control and data signals to desired locations, and controls the functioning of the DSP. The ALU performs arithmetic and logic functions under the control of the ROM, while the serial arithmetic processor section conducts arithmetically complex functions under the control of the ROM. The RAM, under control of the ROM receives and stores data which is sent to the RAM via a system data bus directly from the ROM, from the ALU, from the serial arithmetic processor, and from circuitry exterior to the DSP. The RAM also sends via the data bus data to the ALU, the serial arithmetic processor, the microinstruction sequencer and the circuitry exterior to said digital signal processor under control of the ROM. The provided DSP is particularly advantageous in carrying out ADPCM algorithms.

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