Digital signal processor architecture optimized for performing f

Details Digital signal processor architecture optimized for performing f Digital signal processor architecture optimized for performing f

1997-06-30

1999-08-24

Ngo, Chuong Dinh

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

708404, G06F 738, G06F 1500

Patent

active

059419407

ABSTRACT:
A digital signal processor architecture particularly adapted for performing fast Fourier Transform algorithms efficiently. The architecture comprises dual, parallel multiply and accumulate units in which the output of the multiplier circuit portion of each MAC is cross-coupled to an input of the adder unit of the other MAC as well as to an input of the adder unit of the same MAC to which the multiplier belongs.

REFERENCES:
patent: 3777131 (1973-12-01), Llewellyn
patent: 4354249 (1982-10-01), King et al.
patent: 4612626 (1986-09-01), Marchant
patent: 5038311 (1991-08-01), Monastra et al.

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