Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2001-02-12
2004-05-04
Mai, Tan V. (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S523000
Reexamination Certificate
active
06732132
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a digital signal processor (DSP) for carrying out signal processing under the control of a control processor and a digital signal processing system including the control processor and the DSP.
2. Prior Art
FIG. 1
shows the arrangement of a conventional DSP that carries out signal processing under the control of a control processor. In the figure, symbols C and D designate external registers which are storage means for storing input data to be processed by the DSP, and non-final and final results of the processing.
A multiplication/addition block
100
is connected to the external registers C and D via buses
13
and
14
. The multiplication/addition block
100
is comprised of a multiplication/addition unit
10
for executing arithmetic (or arithmetic-logic) operations on input data supplied via the buses
13
and
14
, and two accumulators ACC
0
and ACC
1
for storing results of the arithmetic operations by the multiplication/addition unit
10
.
The multiplication/addition unit
10
is comprised of two internal registers A and B, a multiplier
11
, and an ALU (arithmetic-logic unit)
12
. The internal registers A and B are for temporarily storing input data to be used in the arithmetic (or arithmetic-logic) operations by the ALU
12
. Input data used for a multiplication operation is supplied to the multiplier
11
necessarily via the bus
13
or
14
through the internal register A or B, while input data for an arithmetic (or arithmetic-logic) operation other than a multiplication is supplied to the ALU
13
via the bus
13
or
14
through the internal register A or B.
The ALU
12
carries out arithmetic (or arithmetic-logic) operations on input data supplied from the internal registers A, B, the multiplier
11
and/or the accumulators ACC
0
, ACC
1
. The accumulators ACC
0
, ACC
1
are for storing results of the arithmetic operations by the ALU
12
. The data written into the accumulators ACC
0
, ACC
1
are delivered to the bus
14
or again input to the ALU
12
.
In
FIG. 1
, the buses and other signal lines are shown with numerals, such as 24 and 48, which indicate the bit widths of these signal lines. As shown in the figure, the buses
13
,
14
and the output signal lines from the internal registers A, B each have a bit width of 24 bits, while a signal line from the multiplier
11
, which outputs results of multiplication of 24-bit data by 24-bit data, has a bit width of 48. A signal line from the ALU
12
, which occasionally accumulates output data from the multiplier
11
, i.e. a result of a multiplication operation thereof, which has a bit width of 48 bits, has a bit width of 56 with an overhead of 8 bits added to the bit width of the output data from the multiplier
11
.
The component elements and parts of the DSP described above are controlled by a program stored in advance in memory means, by so-called pipeline control. That is, assuming, for instance, that the DSP carries out convolution of time-series sample data with a predetermined sequence of filter coefficients, this convolution operation is carried out in the following manner:
First, at a certain clock timing, the multiplier
11
multiplies a first set of sample data and a coefficient stored in the internal registers A and B, respectively, and delivers a result of the multiplication (first multiplication) to the ALU
12
. At the same time, a second set of sample data and a coefficient are written into the internal registers A and B, respectively.
Then, at the next clock timing, the result of the first multiplication is written from the ALU
12
e.g. into the accumulator ACC
0
, and at the same time a result of multiplication of the second set of the sample data and the coefficient (second multiplication) is supplied from the multiplier
12
to the ALU
12
and further a third set of sample data and a coefficient are written into the internal registers A and B.
Then, at the next clock timing, the result of the first multiplication delivered from the accumulator ACC
0
and the result of the second multiplication delivered from the multiplier
11
are added together (i.e. accumulated) by the ALU
12
, and a result of this addition is written into the accumulator ACC
0
. At the same time, a result of multiplication of the third set of the sample data and the coefficient (third multiplication) is delivered from the multiplier
11
to the ALU
12
, and further a fourth set of sample data and a coefficient are written into the internal registers A and B.
Hereafter, multiplication of sample data and a coefficient, and accumulation of a result of the multiplication are repeatedly carried out in the same manner. Then, when multiplication operations of all sets of sample data and coefficients and accumulation of all results of the multiplication operations are completed, a result of this convolution operation, which is obtained at this time point as contents of the accumulator ACC
0
, is delivered to the bus
14
, from which it is supplied to an external device.
Thus, arithmetic operations constituting a convolution operation, such as a multiplication operation and an addition operation, are carried out in parallel by respective devices, which enable the arithmetic operations to be executed efficiently.
Although the operation of the DSP is described above by referring to an example of the convolution operation, there is a case where a further multiplication operation is carried out on output data from the multiplication/addition unit
10
, depending on kinds of arithmetic processing to be carried out. In this case, the output data from the multiplication/addition unit
10
is delivered via the accumulator ACC
0
or ACC
1
to the bus
14
, from which it is written into the internal register A or B of the multiplication/addition unit
10
.
In the conventional DSP, when the ALU
12
has carried out an arithmetic operation, the ALU
12
cannot start the next arithmetic operation before a result of the arithmetic operation is stored in the accumulator ACC
0
or ACC
1
. Therefore, if the ACLU
12
has completed an arithmetic operation before results of its preceding arithmetic operations written into the accumulators ACC
0
and ACC
1
are transferred to another device, the ACLU
12
cannot write the result of the new arithmetic operation into any of the accumulators ACC
0
and ACC
1
, so that the ALU
12
has to wait starting the next arithmetic operation until the accumulator ACC
0
or ACC
1
becomes available.
Further, some kinds of arithmetic processing require lots of arithmetic operations to be executed within a predetermined time period. When such a kind of arithmetic processing is executed by the DSP, if the start of the next arithmetic operation is delayed due to unavailability of the accumulators ACC
0
and ACC
1
, there can be a case where all the required arithmetic operations cannot be completed within the predetermined time period. Conventionally, in such a case, data stored in one accumulator ACC
0
or ACC
1
is transferred to one of the external registers C and D, and a result of an arithmetic operation by the ALU
12
is stored in the one accumulator ACC
0
or ACC
1
which is made available by the transfer of the data therefrom, thereby enabling the ALU
12
to start the next arithmetic operation. In general, however, an accumulator of this kind has a bit accuracy corresponding to the bit width of 56 bits which is higher than a bit accuracy required of data processed by the DSP, which corresponds to the bit width of 24 bits, and hence if the contents of the accumulator are once written into an external register, this degrades the bit accuracy of the data, and in the worst case the data itself can be lost.
Further, there can be a case where the accumulator ACC
0
or ACC
1
suffers from an overflow during processing by the DSP. If the contents of this accumulator are delivered to the bus
14
, the data can be lost by operation of an overflow-protect circuit if it is arranged in the path of delivery of the contents of the accumu
Mai Tan V.
Morrison & Foerster / LLP
Yamaha Corporation
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