Digital signal processing unit having three buses for simultaneo

Details Digital signal processing unit having three buses for simultaneo Digital signal processing unit having three buses for simultaneo

1995-10-24

1998-10-13

Lall, Parshotam S.

395840, G06F 1300

Patent

active

058226133

ABSTRACT:
A digital processor enables data to be read from an external memory without losing arithmetic processing efficiency. A coefficient memory 16, a general-use memory 20, an arithmetic logic unit 26, a sum of products computer 28, a program memory 32, and a host interface circuit 34 are coupled to a data bus 10. A data memory 18, the general-use memory 20, an external memory input/output interface circuit 22, an audio/interface circuit 24, the arithmetic logic unit (ALU) 26, and the sum of products computer 28 are coupled to another data bus 12. The general-use memory 20, the external memory input/output interface circuit 22, and the arithmetic logic unit 26 are coupled to a general data bus 14.

REFERENCES:
patent: 4038642 (1977-07-01), Bouknecht et al.
patent: 5136701 (1992-08-01), Kawai et al.
patent: 5313587 (1994-05-01), Patel et al.
patent: 5504916 (1996-04-01), Murakami et al.
patent: 5566306 (1996-10-01), Ishida

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