Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...
Reexamination Certificate
1997-11-06
2002-09-17
Nguyen, Hiep T. (Department: 2187)
Electrical computers and digital processing systems: processing
Processing architecture
Microprocessor or multichip or multimodule processor having...
C710S316000, C710S317000, C710S052000, C710S053000, C711S148000, C712S020000
Reexamination Certificate
active
06453409
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a digital signal processing system including a control processor and a signal processor for carrying out signal processing under the control of the control processor.
2. Prior Art
The DSP (Digital Signal Processor) is a dedicated processor for signal processing which is capable of carrying out multiplication and/or addition at a high speed. Recently, to realize a DSP capable of exhibiting an even higher level of function, there has been proposed a digital signal processing system of a multiple processor type which has a control processor connected to a DSP to thereby cause the DSP to carry out signal processing operations under the control of the control processor.
FIG. 1
shows an example of the arrangement of a digital signal processing system of this kind which has a CPU (Central Processing Unit,)
1
as a control processor and a DSP
2
as a dedicated. signal processor. Further, a RAM (Random Access Memory)
3
is connected to the CPU
1
and a RAM
4
to the DSP
2
, for storing control information and information for arithmetic operations supplied to and from the processors.
The illustrated digital signal processing system carries out various signal processing operations by the DSP
2
under the control of the CPU
1
. Information (e.g. a program) for signal processing executed by the DSP
2
and signals to be processed by the same are supplied from the CPU
1
to the DSP
2
.
To transfer data between the CPU
1
and the DSP
2
, there are provided data-passing RAM's
5
and
6
between the CPU
1
and the DSP
2
whereby information required by the DSP
2
is supplied from the CPU
1
via these RAM's.
The conventional digital signal processing system is capable of carrying out various signal processing operations by using the DSP
2
, as described above. A large amount of information is required to be transferred from the CPU
1
to the DSP
2
, depending on the contents of the signal processing. However, the data-passing RAM's
5
and
6
are limited in their storage capacity, and if the whole data storage area of the data-passing RAM's
5
and
6
is occupied by data to be transferred between the CPU
1
and the DSP
2
, new data cannot be transferred between the processors, impeding in the worst case smooth execution of the intended signal processing. Thus, the conventional digital signal processing system suffers from the problem that the kinds of signal processing that are executable are limited by the storage capacity of the data-passing RAM's. Further, if the conventional digital signal processing system suffers from a hitch in the data transfer as mentioned above, the processor sending out the data has to wait until at least one of the data-passing RAM's is made available, which degrades the efficiency of the whole system.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a digital signal processing system which is capable of freely passing data between a control processor and a signal processor without being limited by the storage capacity of RAM's.
To attain the above object, according to a first aspect of the invention, there is provided a digital signal processing system comprising a control processor, a signal processor that carries out signal processing under control of the control processor, a plurality of memories, and a connecting device that connects each of the memories selectively to one of the control processor and the signal processor in response to an instruction from the control processor.
Preferably, when data are to be transferred from the control processor to the signal processor, the control processor causes the connecting device to connect one of the memories to the control processor to store the data in the one of the memories, then causes the connecting device to connect the one of the memories to the signal processor, and instructs the signal processor to start processing the data stored in the one of the memories, and if a remaining portion of the data is to be transferred from the control processor to the signal processor and at the same time another one of the memories is available after the instructing the signal processor, the control processor causes the connecting device to connect the another one of the memories to the control processor, and starts storing the remaining portion of the data in the another one of the memories.
Preferably, the digital signal processing system includes a first address bus and a first data bus both connected to the control processor, a second address bus and a second data bus both connected to the signal processor, and the connecting device comprises a first selector provided for each of the memories, for connecting each of the memories selectively to one of the first address bus and the second address bus, a second selector provided for each of the memories, for connecting each of the memories selectively to one of the first data bus and the second data bus, and a controller that delivers a selection instructing signal to the first selector and the second selector of each of the memories under control of the control processor.
More preferably, the first selector comprises a selector for upper places of an address and a selector for lower places of the address, the connecting device including an address decoder interposed between the selector for the upper places of the address and a corresponding one of the memories, the address decoder supplying a chip select signal to the corresponding one of the memories when an address supplied from the selector for the upper places of the address is indicative of the corresponding one of the memories.
Preferably, the memories comprise RAM's.
Preferably the memories comprise RAM's and ROM's.
More preferably, the digital signal processing system includes a plurality of I/O units, the connecting device including a third selector for connecting each of the I/O units selectively to one of the first address bus and the second address bus, and a fourth selector for connecting each of the I/O units selectively to one of the first data bus and the second data bus.
To attain the above object, according to a second aspect of the invention, there is provided a storage medium storing a program executable by a control processor of a digital signal processing system including the control processor, a signal processor that carries out signal processing under control of the control processor, and a plurality of memories, the program comprising a module for causing one of the memories to be connected to the control processor when data are to be transferred from the control processor to the signal processor, a module for causing the one of the memories to be connected to the signal processor after the data has been stored therein, a module for instructing the signal processor to start processing of the data stored in the one of the memories, and a module for, if a remaining portion of the data is to be transferred from the control processor to the signal processor and at the same time another one of the memories is available after the instructing the signal processor, causing the one of the memories to be connected to the control processor, and starting storing of the remaining portion of the data in the another one of the memories.
The above and other objects, features, and advantages of the invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.
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Nguyen Hiep T.
Pillsbury & Winthrop LLP
Yamaha Corporation
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