Digital signal processing method and apparatus

Coded data generation or conversion – Digital code to digital code converters – To or from differential codes

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341143, 341141, H03M 732

Patent

active

057933162

ABSTRACT:
A digital signal processing method and apparatus in which no noise is produced when switching between an original sigma-delta modulated signal and a sigma-delta re-modulated signal obtained on sigma-delta modulation of the original sigma-delta modulated signal. In a digital signal processing device 1a, delay line 3 delays the original sigma-delta modulated signal from an input terminal 2 by a pre-set number of samples. A sigma-delta modulator 6 sets the first-stage feedback loop to next stage feedback loop gain ratio to an integer and outputs a sigma-delta re-modulated signal. A bit length converter 5 matcthes the amplitude level of the original sigma-delta modulated signal entering the sigma-delta modulator 6 to the amplitude level of a feedback signal to a first-stage integrator employed in the sigma-delta modulator 6. On reception of a switching control signal S.sub.D from an input terminal 7, the digital signal processing device 1 causes a pattern coincidence detector 28 to detect pattern coincidence between the original 1-bit signal S.sub.A delayed by the delay line 3, having a number of taps corresponding to the gain ratio, and a sigma-delta re-modulated 1-bit signal S.sub.B, to output a detection signal S.sub.T. This allows a switching controller 29 to control switching of a changeover switch 4 to output a signal changed over from S.sub.A to S.sub.B at an output terminal 8.

REFERENCES:
patent: 5231636 (1993-07-01), Rasmussen
patent: 5345233 (1994-09-01), Nagata et al.
patent: 5627536 (1997-05-01), Ramirez

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