Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...
Reexamination Certificate
1998-10-08
2001-02-13
Donaghue, Larry D. (Department: 2783)
Electrical computers and digital processing systems: processing
Processing architecture
Microprocessor or multichip or multimodule processor having...
C712S036000, C084S626000, C084S732000
Reexamination Certificate
active
06189085
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a digital signal processing device which performs a variety of digital signal processings.
2. Prior Art
As pertaining to the conventional digital signal processing devices, the digital signal process (i.e., DSP) is known. The DSP is advantageous in performing a variety of digital signal processings at high speed. Normally, the DSP contains an arithmetic unit which performs arithmetical operations such as addition and multiplication. As compared to other potions of the DSP, the arithmetic unit is disadvantageous in that the processing speed, particularly the processing speed of the multiplier, is relatively slow. In order to cope with the disadvantage, the pipeline processing is employed to perform the operations.
However, employment of the pipeline processing results in the restriction to the programming for the conventional DSP which uses a plenty of microprograms. In general, the execution speed of the multiplier provided in the arithmetic unit is lower than the execution speed to perform one step of the microprogram; in other words, a certain amount of execution time, which is larger than an execution time required for executing one step of the microprogram, is required to yield a result of multiplication. This means that the result of multiplication cannot be used immediately in the step next to the step which achieves the multiplication instruction. In short, the conventional DSP is disadvantageous in that the processing cannot be performed continuously.
Now, assuming the case where an arithmetical operation for an equation “a×b×c” is performed under the condition where two steps are required to yield the result of multiplication, for example. In that case, if the multiplication of “a×b” is performed in first step, a result of that multiplication an be obtained not in second step but in third step. Therefore, the next multiplication using the number ‘c’ should be performed on the result of the multiplication of “a×b”, which is retained in a register, in third step or later. For this reason, the second step is useless in terms of the execution of the above arithmetical operation; actually however, the second step can be used for executing another instruction. Since the arithmetic unit, containing the multiplier, employs the pipeline processing, the multiplication instruction can be provided for the second step.
As described above, the conventional DSP suffers from a problem that the programming for the microprogram cannot be made continuously. If the DSP uses a high-speed multiplier which is capable of performing the multiplication within one step, the above problem may be eliminated. However, such multiplier is very expensive in cost. In addition, the above problem can be solved by reducing the number of steps of the microprogram which are carried out in one sampling period. However, this will deteriorate the performability of the DSP because in general, the performability of the DSP is improved by increasing the number of steps of the microprogram to be carried out in one sampling period.
When creating the microprogram for the conventional DSP, the designer should create it by paying attention to the timings to yield the results of multiplication. So, codes of different operations should emerge in turn in the microprogram. This badly affects the readability for the microprogram. In short, it takes much time in debugging the microprogram.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a digital signal processing device which can offer a good readability for the microprogram.
The present invention generally relates to the digital signal processing device and particularly to the DSP whose arithmetic unit can be used efficiently. More particularly, the present invention relates to improvement in creating the microprogram.
According to the present invention, the digital signal processing device contains an arithmetic unit which is configured by at least an adder and a multiplier. There are provided first and second microprograms, each of which consists of microinstructions and each of which is designed to perform a specific kind of digital signal processing. The first and second microprograms are alternatively selected in accordance with a preset sequence of processing; and consequently, data supplied to the arithmetic unit are changed in response to the microprogram selected. Thus, the arithmetic unit performs arithmetical operations, using the data selectively supplied thereto, in accordance with the microprogram selected. By changing the sequence of processing, it is possible to change a manner of digital computing performed by the digital signal processing device. For example, the first and second microprograms are executed successively in a serial manner or are executed simultaneously in a parallel manner. Preferably, the first microprogram is designed to impart distortion to the data, while the second microprogram is designed to impart reverberation to the data.
REFERENCES:
patent: 5410603 (1995-04-01), Ishiguro et al.
patent: 5630130 (1997-05-01), Perotto et al.
patent: 5991873 (1999-11-01), Seto et al.
patent: 56-67453 (1979-11-01), None
patent: 62-20032 (1985-07-01), None
patent: 62-44835 (1985-08-01), None
patent: 62-147531 (1985-12-01), None
patent: 61-20892 (1986-05-01), None
patent: 5-150977 (1991-09-01), None
patent: 5-108341 (1991-10-01), None
patent: 5-181668 (1991-12-01), None
patent: 4-195197 (1992-07-01), None
patent: 5-53572 (1993-03-01), None
patent: 5-143075 (1993-06-01), None
patent: 5-150977 (1993-06-01), None
patent: 5-181668 (1993-07-01), None
patent: 5-313682 (1993-11-01), None
“Microprocessor, Microprogram And Control Device” Shoda and Kida; Electronics Science Series—77, Apr. 10, 1978.
Donaghue Larry D.
Morrison & Foerster / LLP
Yamaha Corporation
LandOfFree
Digital signal processing device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Digital signal processing device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Digital signal processing device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2578413