Television – Image signal processing circuitry specific to television
Patent
1993-05-12
1996-02-27
Groody, James J.
Television
Image signal processing circuitry specific to television
348607, 348441, H04N 514
Patent
active
054952964
ABSTRACT:
In order to thin an input signal a second multiplexer is switched to output an output of a first adder and a third multiplexer is switched to output an output of a second adder, and a first multiplexer is alternatively switched at every line. A delay circuit memorizes the sum of the two preceding input signals, and the second adder outputs at every other line the sum of image data of a present line and the two preceding lines. To interpolate an input signal, the second multiplexer is switched to output the output of the delay circuit, the first multiplexer is alternatively switched to output either the input signal or the output of the second multiplexer, and the second multiplexer is alternatively switched to output either the output of the first adder or the output of the delay circuit. Thus, the delay circuit outputs at every other line the sum of the two preceding input signals. Because only one delay circuit is needed the size of the perpendicular thinning/interpolation circuit for an image signal is reduced.
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Van Buul et al., "Standards Conversion of a Videophone Signal with 313 Lines into a TV Signal with 625 Lines", Philips Res. Repts. 29, vol. 29, pp. 413-428, 1974.
Van Buul et al., "Standards Conversion of a TV Signal with 625 Lines into a Videophone Signal with 313 Lines", Philips Res. Repts. 28, pp. 377-390, 1973.
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Dosho Shiro
Juri Tatsuro
Grant Chris
Groody James J.
Matsushita Electric - Industrial Co., Ltd.
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