Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...
Reexamination Certificate
2001-03-29
2004-03-09
Coleman, Eric (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Microprocessor or multichip or multimodule processor having...
C709S216000
Reexamination Certificate
active
06704853
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a digital signal processing apparatus and a method for controlling the apparatus that allow for a fast operation in system control.
BACKGROUND ART
Generally in the field of system control such as servo control, efforts are made to minimize an error between an actual output and an expected target value provided from a device to be controlled. In recent years, a, digital signal processor (hereinafter abbreviated to D{overscore (S)}P) has been widely used, which accepts such an error as a digital value and performs operations on the digital value to generate an optimal manipulated variable for the device to be controlled.
Operations in some DSPs are implemented by hardware tailored to a particular use. However, many DSPs have a configuration in which the operations are controlled by a program. The DPS, like a microprocessor, performs processing according to a given program and is characterized by more sophisticated operations at higher speed than the microprocessor.
FIG. 5
shows an internal configuration of a conventional DSP. In
FIG. 5
, a program counter
2
, in which any value can be set through an external bus
1
, generates a read address of program memory
3
when a process by the DSP is activated. When a jump instruction is detected in an instruction decoder
4
, the jump address is set in the program counter
2
. Otherwise, the counter is incremented by one in synchronization with a system clock.
A program is written into the program memory
3
through the external bus
1
and a program word at the address output by the program counter
2
is output from the program memory
3
.
When a process by the DSP is activated, the instruction decoder
4
interprets the program word provided from the program memory
3
and generates a control signal
9
for controlling internal components, a data memory store address provided to a delay unit
8
, and a data memory read address for reading data X, Y to be input into an arithmetic and logic unit
6
from a data memory
5
.
The control signal
9
is a signal for controlling the arithmetic and logic unit
6
, data memory
5
, and delay unit
8
in the DSP.
The delay unit
8
temporarily holds the data memory store address generated by the instruction decoder
4
and transfers it to the data memory
5
after a wait for a predetermined period of time.
The predetermined time period represents delay time until the arithmetic and logic unit
6
outputs resultant data of an operation specified by an instruction.
The data memory
5
is configured so as to be capable of storing data provided through the external bus
1
and has the capability of outputting data to the arithmetic and logic unit
6
according to the data memory read address and the capability of storing data output by the arithmetic and logic unit
6
according to the data memory store address provided from the delay unit
8
.
The arithmetic and logic unit
6
has arithmetic capabilities for supporting operation instructions in a program stored in the program memory
3
.
A MUX
7
b
selects the result of an operation performed by the arithmetic and logic unit
6
to transfer it to the data memory
5
when the result of the operation is written into the data memory
5
after the instruction decoder
4
detects an operation instruction, or selects an external status signal
10
to transfer it to the data memory
5
when the external status signal
10
is written into the data memory
5
after the instruction decoder
4
detects an external input instruction.
FIG. 6
shows an example of a process that requires time for processing other than operations in servo control processing. In
FIG. 6
, an error
11
is a difference between an actual output and an expected output from a device to be controlled. A manipulated variable
13
is information for operating the controlled device.
Because the error
11
is input into process A in certain cycles, the time for generating the manipulated variable
13
based on the error
11
is limited. The following process should be performed within the limited time.
First, in process A, an operation is performed based on the error
11
and one of the result of the operation and a value of variable
1
(Z
1
) is selected by a selection unit
12
and provided to process B.
Process B performs an operation based on the value selected by the selection unit
12
, stores the intermediate result of the process
1
based on the result of the operation into variable
1
(Z
1
), and outputs the final result of the process
1
as a manipulated variable
13
. Z
1
input into the selection unit
12
is a value on which an operation was performed and stored in variable
1
by process
1
a cycle before.
The manipulated variable
13
calculated in the above-described method is used for driving the device to be controlled in such a way that the manipulated variable
13
is read through the external bus
1
and input into an output circuit such as a digital-analog converter, for example.
In the above-describe example, it is assumed that the external status signal
10
shown in
FIG. 5
is a one-bit signal and that the output from process A is selected by the selection unit
12
shown in
FIG. 6
if the external signal
10
is 0, or Z
1
is selected by the selection unit
12
shown in
FIG. 6
if the external status signal
10
is 1.
FIG. 7
shows part of a program flow in the case where the exemplary process shown in
FIG. 6
is processed by the DSP shown in FIG.
5
. The program flow, “process A→
21
→
22
→
23
→
24
→
25
→
26
→process B”, in
FIG. 7
embodies the flow, “process A→selection unit
12
→process B” shown in FIG.
6
and each of the instructions is transferred from the program memory
3
to the instruction decoder
4
.
First, an external status signal
10
is stored at address K of the data memory
5
by the execution of the external input instruction
21
. Then, the value at address K of the data memory
5
and a comparison value in an operand in the compare instruction
22
are transferred from the data memory
5
to the arithmetic and logic unit
6
, where these values are compared. If they match, an address value existing in the data transfer instruction
26
is set in the program counter
2
by the execution of the conditional jump instruction
23
, and then an output value process A is stored at address T of the data memory
5
by the execution of the data transfer instruction
26
.
If the values do not match in the comparison process by the compare instruction
22
, the program counter
2
is implemented by one, a value in variable
1
(Z
1
) is stored at address T of the data memory
5
, an address value existing in process B is set in the program counter
2
by the execution of the jump instruction
25
, then control is passed to process B.
In process B, an operation is performed based on the value stored at address T of the data memory
5
. Thus, an input to process B is selected from one of the output value process A and variable Z
1
according to the value of the external status signal
10
. In this example, the longest path of the process by the selection unit
12
is “
21
→
22
→
23
→
24
→
25
” and the process requires at least five system clock cycles.
Furthermore, in this example, one value is selected out of the two values. If a value were to be selected out of N values, the number of instructions
27
in
FIG. 7
would increase by N−2, increasing in the required amount of the program memory
3
and increasing the minimum time for processing by the selection unit
12
by 5×(N−2) system clock cycles. This overhead may cause shortage of time assigned to control process to be performed essentially.
However, a conventional DSP as described above takes time for the process of selecting a variable based on information provided externally in program processing and requires an increased amount of programs, increasing the required amount of program memory
3
.
These problems inhibit an increase in processing speed and i
Imamura Yasushi
Inoue Takao
Watanabe Takahiro
Coleman Eric
Matsushita Electric - Industrial Co., Ltd.
Parkhurst & Wendel L.L.P.
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