Digital signal input buffer circuit having a simple construction

Details Digital signal input buffer circuit having a simple construction Digital signal input buffer circuit having a simple construction

1988-12-29

1990-07-24

Zazworsky, John

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307279, 307530, H03K 03356, H03K 524

Patent

active

049437380

ABSTRACT:
An input buffer circuit includes a flipflop circuit and receives an input voltage signal and a reference voltage to amplify a difference between the input voltage signal and the reference voltage in response to an activation signal. The input buffer circuit comprises first and second transistors having their sources commonly connected to a first node and their drains coupled to a pair of inputs of the flipflop circuit, respectively. A gate of the first transistor is connected to receive the input voltage signal and a gate of the second transistor is connected to receive the reference voltage. A capacitor is connected at its one end to the first node and at its other end to a second node. There is provided a bias control circuit having an output connected to the second node and operating to respond to a precharge signal so as to bring the second node to a first level and to respond to the activation signal so as to bring the second node to a second level lower than the first level, so that the potential of the first node is consequentially lowered when the input buffer circuit executes the comparison operation in response to the activation signal and a current flowing through the first and second transistors is blocked by the capacitor.

REFERENCES:
patent: 4096402 (1978-06-01), Schroeder et al.
patent: 4441039 (1984-04-01), Schuster
patent: 4649293 (1987-03-01), Ducourant

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