Excavating
Patent
1995-09-29
1998-04-28
Baker, Stephen M.
Excavating
371 4014, G11B 2018, H03M 1300
Patent
active
057455058
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a digital signal encoding method and apparatus, a digital signal recording medium, and a digital signal decoding method and apparatus, and is applicable to an apparatus for encoding and decoding a digital signal by adding an error correction code.
BACKGROUND ART
Heretofore, in a compact disc (CD), an audio signal is converted into a digital signal so that the signal is encoded and recorded in accordance with a CD standard. A signal format of the CD is shown in FIG. 14. One frame comprises one byte long subcode, 24 bytes long actual data, and 4 bytes long C1 error correction code and 4 bytes long C2 error correction code (CIRC (Cross Interleave Reed-Solomon Code)) which amount to a total of 33 bytes. In addition, at the head of the one frame, a frame synchronization signal is added. Consequently, a ratio of the error correction codes which occupies in the total size of data excluding subcodes, namely the redundancy is 8 bytes/32 bytes, or 25%.
In addition, in the case of a signal format of the CD, as shown in FIG. 15, one block is formed of 98 frames which is called one sector. Actual data in this one sector is 2352 bytes long. In the two frames long subcode at the head of the one sector, peculiar patterns referred to as S0 and S1 are recorded so that the head of the sector can be differentiated. Incidentally, the error correction code CIRC is what connects two stages of Reed Solomon Codes, namely C1 and C2 codes with the interleave.
A structure of this CD encoding/decoding apparatus is shown in FIG. 16. At the outset, in the encoding apparatus, six samples portion of each channel L and R, or 24 bytes constitutes one unit of the digital audio data so that the data is input to the CIRC encoding circuit 1. The CIRC encoding circuit 1 comprises a circuit shown in FIG. 17. More specifically, an even number sample delay circuit 21 and a scramble circuit 22 delays by two frame portions even-numbered sample data respectively to change the arrangement thereof. This is intended to interpolate defect portion that cannot be corrected with adjacent data and to obscure the data in acoustic sense when the error cannot be corrected.
Furthermore, C2 code encoding portion 23 calculates 4 bytes of C2 parity to be added to the 24 bytes of the original code. The interleaver 24 offers interleaves whose maximum delay extends over 108 frames. The C1 code encoding portion 25 calculates 4 bytes long C1 parity to be added to 28 bytes long data including the original code and C2 parity, so that the total length of data becomes 32 bytes.
The odd number symbol delay circuit 26 delays by another one frame portion only the odd-numbered symbol. The reason for such a delay is that when a random error is generated over 2 bytes the effect is given to only one symbol in one series of C1 codes. The inverter 27 inverts a polarity of the parity to prevent a judgement that no error is generated when an error in all the data becomes zero.
A subcode adding circuit 2 adds one byte long subcode to a CIRC encoding output thus obtained for each of 32 bytes. Here, above-described codes S0 and S1 indicating the head of the sector are also added as the subcodes. And the codes are EFM modulated with the subsequent EFM (Eight Fourteen Modulation) modulating circuit 3, and a frame synchronization signal is added to a head of the frame in the frame synchronization signal adding circuit 4 to be sent to a cutting apparatus 5. The cutting apparatus 5 performs mastering so that a disc 6 in which a digital audio signal is recorded in accordance with the CD standard is manufactured.
On the other hand, the decoding apparatus performs a process which is opposite to the encoding process for decoding the signals. More specifically, the signal read from the disc 6 is separated with a frame synchronization detecting and separating circuit 8 via an RF amplifier 7 with the detection of the frame synchronization signal. Subsequently, the EFM demodulation circuit 9 demodulates the signal, and the subcode detecting and sepa
REFERENCES:
patent: 4356564 (1982-10-01), Doi et al.
patent: 4451920 (1984-05-01), Hoshimi et al.
patent: 4598403 (1986-07-01), Odaka
patent: 5060221 (1991-10-01), Sako et al.
Akiyama Yoshiyuki
Fujinami Yasushi
Igarashi Katsuji
Iwamura Ryuichi
Yonemitsu Jun
Baker Stephen M.
Frommer William S.
Sony Corporation
LandOfFree
Digital signal encoding method and apparatus, digital signal rec does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Digital signal encoding method and apparatus, digital signal rec, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Digital signal encoding method and apparatus, digital signal rec will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1540141