1987-10-01
1989-09-26
Pellinen, A. D.
Excavating
360 48, 360 53, 360 572, G11B 2018
Patent
active
048706477
ABSTRACT:
A digital signal demodulator is provided for demodulating a reproduced recorded modulated digital signal which includes a parity code. The recorded modulated digital signal has a data code format which may include both valid used data codes and unused redundant phantom codes as a result of an industry standard code format conversion. The digital signal demodulator includes a redundant portion detection circuit which detects whether unused redundant phantom codes are present in the reproduced modulated digital signal data, a demodulating circuit which demodulates the reproduced modulated digital signal, an error detection circuit which effects an error detection using a parity code in the demodulated digital signal to detect erroneous data in the demodulated signal, and a judgment circuit which, when unused redundant phantom codes are detected in the modulated digital signal data, judges the corresponding demodulated digital signal data to be erroneous irrespective of the result of the parity code error detection operation.
REFERENCES:
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patent: 4598403 (1986-07-01), Odaka
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patent: 4685004 (1987-08-01), Takahashi et al.
patent: 4697212 (1987-09-01), Osawa et al.
patent: 4710923 (1987-12-01), Nagumo
Hikawa Kazuo
Inoue Yasuo
Evans Geoffrey S.
Pellinen A. D.
Victor Company of Japan
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