Communications: electrical – Digital comparator systems
Patent
1993-06-29
1995-05-02
Wamrach, Margaret Rose
Communications: electrical
Digital comparator systems
G06F 702
Patent
active
054123682
ABSTRACT:
A method of comparing a first multibit digital signal with a second multibit digital signal wherein to increase speed of obtaining an output signal said method comprises inputting input signals for each of said first and second signals and forming a respective codeword for each input signal, each codeword being at least one bit longer than the respective input signal and formed by the same error correcting code for both signals to provide increased minimum Hamming distance for the respective codewords, comparing respective bit locations of the codewords to form a plurality of match indicating signals for respective bit locations thereby indicating any mismatch by a mismatch at at least two bit locations, supplying said match indicating signals in parallel to gating circuitry arranged to provide an output indicating a match or mismatch between said codewords, said output being provided with a time delay less than that required for a single bit mismatch. The invention also provides digital signal comparison circuitry.
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IBM Technical Disclosure Bulletin, vol. 13, No. 6, Nov. 1970, New York, pp. 1657-1658; D. Bossen "Error Checking Means for Associated Memory Map".
IEEE Journal of Solid-State Circuits, vol. SC-11, No. 5, Oct. 1976 New York, pp. 692-695, C. Mead, et al. "128-Bit Multicomparator" p. 693, left column, line 56--right column, line 1; figure 4.
Barnaby Catherine L.
Gammack Richard J.
Stansfield Anthony I.
Inmos Limited
Wamrach Margaret Rose
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