Digital sigma-delta modulators

Coded data generation or conversion – Analog to or from digital conversion – Differential encoder and/or decoder

Reexamination Certificate

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C341S076000

Reexamination Certificate

active

07825842

ABSTRACT:
A digital sigma-delta modulator (100) for modulating a digital input signal (x) is described. The digital sigma-delta modulator (100) comprises a quantizer (115) for quantizing an input signal (s) and producing a quantized output signal (y) at a first output (110) and an error output signal (−q) at a second output (165), at least one feedback loop (120, 125) connected to an input adder (140) and the first outputs (110) and the second output (165) of the quantizer (115) and a feedback filter (130, 135) in the at least one feedback loop (120, 125). The input adder (140) produces the sum signal (s) by adding the digital input signal (x) at an input (105) and output signals of the at least one feedback loop filters (130,135).

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patent: 2408858 (2005-06-01), None
International Preliminary Examinaton Report in PCT/EP2007/004896, Dec. 2008.
Hossack DM et al: “The application of redundant number systems to digital sigma-delta modulators” Circuits and Systems, 1994. ISCAS '94, 1994 IEEE International Symposium on London, UK May 30-Jun. 2, 1994, New York, NY, USA,IEEE, US, vol . 2, May 30, 1994, pp. 481-484, XP010143079 ISBN: 0-7803-1915-X p. 482, left-hand column, lines 8-20.
Roncella R et al: “A VLSI Systolic Adder for Digital Filtering for Delta-Modulated Signals” IEEE Transactions of Acoustics, Speech and Signal Processing, IEEE Inc. New York, US, vol. 37, No. 5, May 1, 1989, pp. 749-754, XP000252731, ISSN: 0096-3518.
Wong et al: “FIR Filters With Sigma-Delta Modulation Encoding” retrieved from the internet on the Aug. 31, 2006 via: http://ieeexplore.ieee.org/iell/29/2024/00056058.pdf?arnumber=56058#search=%22systolic%20filter%20modulation%20sigma&20delat%22. see esp. p. 980 top of second column.

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