Digital .SIGMA.-.DELTA. modulator

Details Digital .SIGMA.-.DELTA. modulator Digital .SIGMA.-.DELTA. modulator

1993-03-30

1994-09-06

Logan, Sharon D.

Coded data generation or conversion

Digital code to digital code converters

To or from differential codes

341 77, H03M 736

Patent

active

053452330

ABSTRACT:
A counter counts a clock signal. A multiplexer sequentially inputs digital input signals each having a plurality of bits in accordance with an output signal from the counter. A subtracter subtracts a quantized output signal delayed by an n-clock delay element from the input signal. An integrator integrates an output signal from the subtracter. The quantizer quantizes an output from the integrator. The n-clock delay element delays the output signal from the quantizer by n clocks and supplies the delayed signal to the subtracter. A demultiplexer sequentially outputs output signals from the quantizer in accordance with the output signal from the counter. This demultiplexer outputs signals in the input order of the multiplexer.

REFERENCES:
patent: 4692737 (1987-09-01), Stikvoort et al.
IEEE Journal Of Solid State Circuits, Jun. 1987, vol.-SC-22-No. 3, pp. 390-394, Peter J. A. Naus, et al., "A CMOS Stereo 16 Bit D/A Converter For Digital Audio."
IEEE Journal of Solid State Circuits, Aug. 1981, vol.-SC-16-No. 4, pp. 333-341, T. Misaw, et al., "Single-Chip Per Channel Codec With Filters . . . ".

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