Digital settable frequency generator with phase-locking loop

Details Digital settable frequency generator with phase-locking loop Digital settable frequency generator with phase-locking loop

1977-04-26

Kominski, John

Oscillators

Automatic frequency stabilization using a phase or frequency...

Tuning compensation

331 1R, 331 14, 331 36C, H03B 304

Patent

active

040204251

ABSTRACT:
A digitally settable frequency generator comprises a master oscillator whose operating frequency f.sub.Q is variable between a normal value f.sub.Q " and a slightly lower value f.sub.Q ' = (1-p)f.sub.Q " with the aid of a normally disconnected tuning capacitor. The master oscillator works into a frequency divider of fixed step-down ratio m:1 (or 2m:1) to produce a reference frequency f.sub.B. A slave oscillator, generating an output frequency f.sub.A = gf.sub.B, is controlled by a phase-locking loop including a phase comparator to which the reference frequency f.sub.B is fed along with a like frequency obtained from output frequency f.sub.A with the aid of another divider having a digitally variable integral step-down ratio g:1. A fractional value i, which may range from 0 to 100%, is set with the aid of a numerical interpolation selector to determine the number n<m of cycles of operating frequency f.sub.Q within a cycle (or half-cycle) of reference frequency f.sub.B during which that operating frequency is changed to its lower value f.sub.Q '. With a division factor of 2m, alternate half-cycles of reference frequency f.sub.B can be used for stabilizing the frequency f.sub.Q with the aid of another phase-locking loop driven by a standard oscillator. Such a division factor also allows the operating frequency of the master oscillator to be held at its normal value f.sub.Q " throughout the first half of every odd-numbered reference-frequency cycle (n=O) and at its reduced value f.sub.Q ' throughout the first half of every even-numbered cycle (n=m), independently of the setting of the interpolation selector which controls that operating frequency only during the remaining half-cycles (n=im); with a switchover from g to g + 1 during each even-numbered cycle, the parameter p can be adapted to changes in the division factor g by periodically adjusting the tuning capacitor in response to an error signal derived from any variation, between consecutive cycles, in the relative phasing of the two oscillations of reference frequency f.sub.B fed to the phase comparator which controls the slave oscillator.

REFERENCES:
patent: 3177442 (1965-04-01), Halverson
patent: 3311841 (1967-03-01), Corney et al.
patent: 3441870 (1969-04-01), Wicker
patent: 3453542 (1969-07-01), Hoffmann
patent: 3713040 (1973-01-01), Page, Jr.
patent: 3864637 (1975-02-01), Kanow

Affiliated with

Also associated with

Rating

Digital settable frequency generator with phase-locking loop does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Digital settable frequency generator with phase-locking loop, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Digital settable frequency generator with phase-locking loop will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2090007