Digital self-calibration of a digital-to-analog converter

Details Digital self-calibration of a digital-to-analog converter Digital self-calibration of a digital-to-analog converter

2001-10-26

2003-03-04

Tokar, Michael (Department: 2819)

Coded data generation or conversion

Converter calibration or testing

C341S118000, C341S144000, C341S138000, C341S153000

Reexamination Certificate

active

06529149

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a digital-to-analog converter. More particularly, the present invention relates to digital self-calibration of a digital-to-analog converter.
BACKGROUND OF THE INVENTION
A digital-to-analog converter (DAC) transforms digital input codes into an analog output signal consisting of a range of analog values. DACs are used in a wide variety of applications including data conversion systems and digital communications systems.
Characteristics that determine the performance quality of a DAC include resolution, sampling rate, linearity and monotonicity. Resolution is the number of bits of digital input code used to produce the corresponding analog output signal. The higher the resolution, the more accurately the digital input can be converted to an analog equivalent. Next, the sampling rate indicates the rate at which the digital input codes are converted to analog outputs. Linearity reflects that for each change in the digital input code, there is a proportionate change in the analog output. If a DAC is ideally linear, then the analog output values will increase uniformly by a constant amount as the values of the digital input increase. “Differential Non-Linearity” is the deviation from ideal linearity of the analog output signal measured between two successive digital input codes. Finally, a DAC exhibits monotonicity if in its transfer characteristic (a graph of the analog output as a function of the digital input), increasing digital input results in increasing analog output, i.e., as the values of the digital input codes increase, the values of the analog outputs never decrease. Thus, a DAC exhibits nonmonotonicity if an incremental increase in the digital input results in an incremental decrease in the analog output.
A number of DAC designs are well-known in the art. One such design is a binary-weighted DAC, which converts digital input code to an analog output by assigning a weight to each bit in the digital input code, and summing the of the entire code.
FIG. 1
shows a current-steering DAC with the most significant bit (MSB) stage based on radix a, and the remaining stages based on radix 2. The following polynomial expresses the total analog output, I
out
, of the current-steering DAC in FIG.
1
:
I
out
=(
I
/2
N
)(
b
N
a
N−1
+b
N−1
2
N−2
+. . . b
2
2
1
+b
1
2
0
),
where N is the number of bits (each represented by a current source) contained in the digital input code. The quantity a is the radix of the MSB stage. When a equals 2, the result is a binary-weighted current-steering DAC. When a is other than 2, the result is a non-radix 2 current-steering DAC. The bit coefficients b
1
, b
2
, etc., are either 1 or 0 as the current source is switched (or steered) to direct the current. A current source is steered to ground for a 0, or through the circuit for a 1, depending on whether the bit of digital input code represented by the current source is a 0 or a 1. Among the bit coefficients, b
N
is bit coefficient for the MSB, while b
1
is bit coefficient for the least significant bit (LSB). The term corresponding to the MSB, b
N
a
N−1
, is based on radix a, while the terms of the other bits are based on radix 2.
FIG. 2A
shows an ideal transfer characteristic of a binary-weighted current-steering DAC. As the polynomial above illustrates, the total analog current output of a current-steering DAC can be expressed as a linear combination of the current sources. Ideally, the current source ratios are exactly a factor of 2, in which case the DAC is binary-weighted and its transfer characteristic is ideal, as shown in FIG.
2
A. As stated previously, a binary-weighted DAC results when a=2 in the above polynomial.
FIG. 2B
shows the effect on the transfer characteristic when a<2 in the above polynomial. When a<2, errors are introduced in the analog output of the current-steering DAC. The errors result in, among other things, nonlinearity and nonmonotonicity in the transfer characteristic of the DAC. When a<2, the transfer characteristic is monotonic until the MSB changes from a 0 to a 1. When the MSB changes from a 0 to a 1, the analog output jumps in the negative direction, introducing nonmonotonicity and nonlinearity in the transfer characteristic of the DAC. The nonmonotonicity and nonlinearity occur only at the MSB transition from a 0 to a 1. After the transition, the transfer characteristic is again monotonic and linear.
When a<2, the DAC is referred to as a reduced-radix DAC. In traditional DACs, analog calibration methods are used to avoid the reduced-radix situation, and achieve high resolution (e.g., 12-bit or higher resolution). However, analog calibration methods require special procedures, processes and layouts. In addition, changes in the operating environment, such as a change in temperature, over the life of the DAC may alter the analog calibration.


REFERENCES:
patent: 4336526 (1982-06-01), Weir
patent: 4465996 (1984-08-01), Boyacigiller et al.
patent: 4843392 (1989-06-01), Gulczynski
patent: 5499027 (1996-03-01), Karanicolas et al.
patent: 5517191 (1996-05-01), Wynne
patent: 5583501 (1996-12-01), Henrion et al.
patent: 5666118 (1997-09-01), Gersbach
patent: 5668549 (1997-09-01), Opris et al.
patent: 5703582 (1997-12-01), Koyama et al.
patent: 5929796 (1999-07-01), Opris et al.
patent: 6130632 (2000-10-01), Opris
patent: 6348885 (2002-02-01), Munoz et al.
Z. Boyacigiller, et al., “An Error-Correcting 14-b/20 u s CMOS A/D Converter,” in Proc. IEEE Int. Solid-State Circuits Conf., 1981, pp. 62-63, ISSN: 0193-6530, Publisher: Lewis Winner, FL, USA.
A.B. Grebene, “Bipolar and MOS Analog Integrated Circuit Design: Chapter 14: Data Conversion Circuits: Digital-To-Analog Converters,” 1984, pp. 753-824, Publisher: Wiley, NY, USA.
H.-Seung Lee, et al., “A Self-Calibrating 15-b CMOS A/D Converter,” Dec. 1984, IEEE J. Solid-State Circuits, vol. SC-19, No. 6, pp. 813-819.
A. N. Karanicolas, et al., “A 15-b 1-Msample/s Digitally Self-Calibrated Pipeline ADC,” Dec. 1993, IEEE J. Solid-State Circuits, vol. SC-28, No. 12, pp. 1207-1215.

Affiliated with

Also associated with

Rating

Digital self-calibration of a digital-to-analog converter does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Digital self-calibration of a digital-to-analog converter, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Digital self-calibration of a digital-to-analog converter will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3058798