Digital self-calibrating delay line and frequency multiplier

Details Digital self-calibrating delay line and frequency multiplier Digital self-calibrating delay line and frequency multiplier

1991-12-20

1993-06-01

Ng, Jin F.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307602, 328 15, H03K 513, H03B 1900

Patent

active

052163016

ABSTRACT:
A digital self-calibrating delay line is disclosed wherein in a chain of individual but identical time delay elements a calibrated signal running therethrough is compared with the subsequent input signal on each of the individual time delay elements until a coincidence time delay element is determined at which time an output is indicated. The period of the calibrating signal is chosen to be equal to the delay to be imparted to a signal to be delayed. Prior to or upon the appearance of the signal to be delayed, the calibration signal is removed and the incoming signal inserted into the time delay chain to output at the individual time delay element determined by the calibration signal. In an alternate embodiment, by the addition of a few components to each of the time delay elements, the subject invention is interconnected to output a signal whose frequency is a multiple of the input signal. Such is accomplished by directing the output of the coincidence time delay elements to selected (prior in line) time delay elements to output frequency pulses at proper intervals in the original input pulse time period to achieve the frequency multiplication.

REFERENCES:
patent: 3622809 (1971-11-01), Williams
patent: 4233525 (1980-11-01), Takahashi et al.
patent: 5049766 (1991-09-01), Van Driest et al.

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