Digital receiver using equalization and block decoding with eras

Details Digital receiver using equalization and block decoding with eras Digital receiver using equalization and block decoding with eras

1996-08-22

1998-01-13

Chung, Phung

Excavating

371 41, 371 45, 371 391, 375229, G06F 1100

Patent

active

057086656

ABSTRACT:
A communications receiver system is presented for detecting burst errors and providing erasure information to the block decoder (outer decoder), thereby effectively doubling the conventional correction capability of the block decoder with only a minimal increase in complexity. In one embodiment, this mechanism takes the form of a circuit which re-encodes the output of the inner decoder, compares it with the received sequence of code symbols, and flags a portion of the inner decoder output for erasure when an excessive number of code symbol errors are detected. In a second embodiment, this mechanism takes the form of a circuit which makes hard symbol decisions on the channel signal, compares the hard decisions to the channel signal to determine a noise level, and thereafter flags the channel output in regions with excessive noise levels.

REFERENCES:
patent: 4829525 (1989-05-01), Sugiyama et al.
patent: 5430743 (1995-07-01), Marturano et al.

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