Pulse or digital communications – Receivers – Automatic baseline or threshold adjustment
Reexamination Certificate
1998-06-11
2001-08-14
Bocure, Tesfaldet (Department: 2731)
Pulse or digital communications
Receivers
Automatic baseline or threshold adjustment
C359S199200
Reexamination Certificate
active
06275541
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a digital receiver circuit. More particularly to a photo receiver circuit in a form of IC for an optical data link.
2. Description of the Related Art
In a transmitter and receiver of an optical data link, speeding-up, down-sizing, lowering of cost, power saving, providing wider reception dynamic range corresponding to a transmission line of plastic optical fiber being inexpensive and having large loss, have been demanded.
A construction of the conventional wide reception dynamic range photo receiver circuit is illustrated in FIG.
5
. The shown conventional circuit is constructed with a photodiode
1
, a pre-amplifier portion
15
and a post amplifier portion
16
. Then, the pre-amplifier portion
15
and the post amplifier portion
16
are connected by way of an alternating current coupling employing a capacitor
23
.
The pre-amplifier portion
15
has been disclosed in Japanese Unexamined Patent Publication (Kokai) No.Showa 62-257204. The pre-amplifier portion
15
is constructed with an inverting type transimpedance amplifier
11
, an npn type transistor
3
having an emitter connected to an input end of the transimpedance amplifier
11
and a collector connected to a positive power source, an npn type transistor
4
having a collector connected to an input end of the transimpedance amplifier
11
and an emitter connected to a negative power source, a constant voltage source
19
and an operational amplifier
20
performing non-inverting amplification and level shifting for an output of the transimpedance amplifier
11
, a peak detection circuit
17
detecting and holding a peak value of the output of the operational amplifier
20
and outputting to a base of the transistor
3
, a constant voltage source
21
and an operational amplifier
22
performing inverting amplification and level shifting for an output of the transimpedance amplifier
11
, and a peak detection circuit
18
detecting and holding a peak value of the output of the operational amplifier
22
and outputting to a base of the transistor
4
.
The post amplifier portion
16
is constructed with a differential output limiting amplifier
24
and a quantizer
14
outputting one of a logical “1” and a logical “0” depending upon polarity of a differential voltage of a positive-phase output and a negative-phase output of the limiting amplifier
24
.
Next, discussion will be given for an operation of the pre-amplifier portion
15
of the conventional photo receiver circuit with reference to FIG.
6
.
FIG. 6
shows a relationship between an amplitude of a photo current pulse flowing into the photodiode
1
and an output voltage at a point B. A bias is applied so that both transistors
3
and
4
are turned OFF (Tr
3
off, Tr
4
off) when an amplitude of the input current is small, for lowering of noise. Therefore, operation of the pre-amplifier portion
15
becomes linear operation of the inverting type transimpedance amplifier
11
. According to increasing of the amplitude of the input current, a voltage BM at a point B corresponding to a mark portion drops and a voltage BS at a point B corresponding to a space portion becomes constant.
When the amplitude of the input current increases, in an offset control loop constructed with a transistor
4
, a peak detector
18
, a constant voltage source
21
and an operational amplifier
22
, the voltage corresponding to the mark portion is detected by the peak detection circuit
18
. By this, the transistor
4
turns ON (tr
4
on) to maintain the voltage at the point B corresponding to the mark portion. Thus, according to increasing of the amplitude of the input current, the voltage of the point B corresponding to the space is elevated.
When the amplitude of the input current is further increased, in addition to the operation of the foregoing offset control loop, in an input impedance control loop constituted of a transistor
3
, a peak detector
17
a constant voltage source
19
and an operational amplifier
20
, a voltage corresponding to the space portion is detected by the peak detection circuit
17
. By this, the transistor
3
is turned ON (Tr
3
on) to lower an input impedance. Accordingly, an alternating current component of an input current pulse flows to the transistor
3
and a direct current component flows to the transistor
4
so that quite limited amount is input to the transimpedance amplifier
11
. Thus, an automatic gain control is performed for maintaining the voltages BM and BS at the point B respectively corresponding to the mark portion and the space portion constant even if the amplitude of the input current is increased. By this, comparing with the transimpedance amplifier
11
, a dynamic range of the input can be significantly increased.
In the above-mentioned conventional photo receiver circuit encounters the problems to cause difficulty in integration of the pre-amplifier portion and the pose amplifier portion into a single chip and in reduction of number of parts which are inherent for down-sizing, lowering of power consumption and for lowering of price.
Namely, in order to achieve integration into a single chip, it becomes necessary for establishing DC coupling for all of the circuits. However, in the conventional receiver circuit, since the DC level of the output of the pre-amplifier
15
is variable depending upon the amplitude of the input current, an alternating coupling using an external capacitor
23
externally applied to the IC becomes necessary between the pre-amplifier portion and the post amplifier. Therefore, number of parts and power consumption can be increased.
SUMMARY OF THE INVENTION
The present invention has been worked out for solving the problems in the prior art set forth above. Therefore, it is an object of the present invention to provide a digital receiver circuit which can establish DC coupling between all circuits with minimum number of parts and can easily integrated into a single chip.
According to the first aspect of the present invention, a digital receiver circuit including a photoelectric converter element covering an input light into an electric signal, a differential output amplifier circuit receiving an output of the photoelectric converter element and a control circuit controlling an offset and an input impedance of the differential output amplifier circuit, for binarizing decision for the differential output, comprises:
first and second peak detection circuits respectively detecting peak values of the differential output;
a peak difference detection circuit for detecting a difference between two peak values detected by the first and second peak detection circuits;
an offset control circuit controlling offset of the differential output amplification circuit depending upon a result of detection of the peak difference detection circuit;
an average value detection circuit deriving an average value of the two peak values detected by the first and second peak detection circuit;
a comparing circuit comparing derived average value with a predetermined reference voltage; and
an input impedance control circuit for controlling an input impedance of the differential output amplification circuit depending upon a result of comparison of the comparing circuit.
According to the second aspect of the present invention, a digital receiver circuit including a photoelectric converter element covering an input light into an electric signal, a transimpedance amplifier amplifying an output of the photoelectric converter element, a differential output amplifier circuit outputting a result of comparison of an amplified output and a predetermined reference voltage as a differential signal, for binarizing identification for the differential output, comprises:
first and second peak detection circuits respectively detecting peak values of the differential output;
a peak difference detection circuit for detecting a difference between two peak values detected by the first and second peak detection circuits;
an offset control circuit controllin
Kanemitsu Shunichi
Nagahori Takeshi
Bocure Tesfaldet
NEC Corporation
Scully Scott Murphy & Presser
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