Telecommunications – Receiver or analog modulated signal frequency converter – Local control of receiver operation
Reexamination Certificate
2000-09-14
2004-03-02
Trost, William (Department: 2683)
Telecommunications
Receiver or analog modulated signal frequency converter
Local control of receiver operation
C455S265000, C375S327000, C375S364000, C375S371000, C375S376000
Reexamination Certificate
active
06701140
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The invention is related to digital communication devices and in particular to a receive digital phase lock loop.
2. Background Art
Digital communications such as those provided in a wide area network (WAN) or local area network (LAN) of personal computers (for example) are constantly being improved to operate at higher data rates. For example, there is considerable interest in developing networks capable of operating at a clock frequency of 10 MHz, corresponding to a pulse width of 50 nanoseconds (nS). Preferably, the data transmitted on the network is Manchester encoded. The problem with such a high data rate (narrow pulse width) is that the system is particularly susceptible to failure due to distortion of the data stream inherent in any transmission medium, such as cables running between offices in a large building for example. The speed at which the data-containing signal travels through the cable is affected by a number of things including stray capacitances that can vary depending upon surrounding conditions. Such changes cause the signal's speed to vary. Such variations cause jitter in the received signal, in which the time between successive pulses observed at a receiving point in the network fluctuates, causing the apparent position of each pulse to drift. If this drift becomes excessive, the receiving device cannot maintain synchronization between the incoming data stream and its own clock, leading to complete loss of the received signal. For a typical cable, the drift induced by jitter can be exceed 10 nS and can be as great as 13.5 nS. For older systems that operate at lower frequencies (and therefore larger pulse widths), this does not pose a significant problem. However, a 13.5 nS drift in a high-speed system in which the pulse width is only 50 nS, for example, often causes loss of synchronization and therefore failure.
Typically, a digital phase lock loop (PLL) operating at a clock rate many times the frequency of the incoming data maintains synchronization between the incoming data and the receiver, so that the receiver takes only a narrow sample of each pulse near the center of the pulse or at least well away from either edge of the pulse. The time at which each data sample is taken (the data sample point) is controlled by the PLL. The goal of the phase lock loop is to follow the drift in the received signal so as to keep the data sample point in the middle of each successive pulse. I previously developed a high speed digital PLL having a phase error counter and an edge counter. The edge counter counts the number of edges and indicates when the phase lock loop should update its data sample point. The phase error counter tracks the phase of the incoming signal relative to the PLL's current sample data point, and periodically updates this point. At the update time, the phase error counter polarity indicates whether to advance or retard the data sample point by one clock. Upon making this correction, both the phase error counter and the edge counter are cleared, and the process is restarted.
I found that the foregoing architecture, when applied to data having a frequency of 10 MHz, was inadequate to withstand jitter of well over 10 nS, e.g., jitter of 13.5 nS. That is, the architecture was susceptible to synchronization loss in the presence of jitter of 13.5 nS. Since this amount of jitter can be expected in many applications, it is a goal of the present invention to improve this architecture to the point that it can reliably maintain synchronization of 10 MHz data in the presence of 13.5 nS jitter.
One problem with the foregoing architecture is that the selection of the time between updates necessarily involves a tradeoff between two constraints. One constraint is that each block of data is preceded by a preamble of successive uniform pulses, typically about 56 pulses, during which synchronization must be attained before the actual data stream begins. This requirement demands minimizing the time between updates so that the PLL achieves synchronization as quickly as possible. The other constraint is that the PLL be stable and not'susceptible to a temporary phase deviation in the incoming data. This latter requirement demands maximizing the time between updates so that the PLL is fairly insensitive to temporary phase deviations. Thus, it does not appear both requirements can be met together. It is therefore another goal of the invention to establish synchronization very quickly—before the end of the preamble—without sacrificing stability of the PLL.
SUMMARY OF THE INVENTION
A digital phase lock loop (PLL) for maintaining synchronization with the phase of a received data signal including a preamble and an information-containing data frame, by incrementing a state machine through an internal cyclic count, each cycle thereof including a center count tending to coincide with center regions of the successive pulses and an edge count tending to coincide with edges of the successive pulses. The PLL selects a current sample of the signal whenever the internal count reaches the predetermined center count value. The state machine internal count is updated in accordance with a cumulative phase error obtained by summing the phase errors detected over successive edges between each edge and the corresponding center count. The interval over which the cumulative phase error is computed depends upon the number of received edges during the preamble and depends upon elapsed time during the data frame. The advantage is that the interval can be very short during the initial portion of the preamble so that synchronization is obtained quickly before the end of the preamble while the interval is longer during the data frame to optimize stability after synchronization has already been attained.
In addition, during the preamble, as the PLL approaches synchronization, the number of edges in each interval may be increased over successive intervals to increase system stability. For example, starting with a minimum number of edges (2), the number of edges per interval may double with each successive interval. Preferably, during the data frame, the interval is a constant time duration which is very long relative to the intervals selected during the preamble.
REFERENCES:
patent: 5811998 (1998-09-01), Lundberg et al.
patent: 5812619 (1998-09-01), Runaldue
patent: 5896067 (1999-04-01), Williams
patent: 5943378 (1999-08-01), Keba
patent: 6282042 (2001-08-01), Hana
3Com Corporation
Michaelson Peter L.
Michaelson & Associates
Miller Brandon
Trost William
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