Digital real-time signal processor

Details Digital real-time signal processor Digital real-time signal processor

1982-10-21

1986-12-02

Shaw, Gareth D.

Boots, shoes, and leggings

364736, G06F 1300, G06F 1500

Patent

active

046270264

ABSTRACT:
A digital real-time signal processor is designed to be coupled to a computer. This processor includes a circuit of inputs/outputs, an input/output control circuit, a computer-coupling circuit, a buffer memory, digital signal-processing elements and a control circuit for the processing elements. The digital signal-processing elements are made up of a plurality of interconnected processing modules. Each module comprises an arithmetic unit, a high-speed multiplier, a shift register, a function memory, an addressable data memory containing all data handled by the processors of various functions, a sequentially operated address memory enabling scanning the data memory, and a microprogram memory. Each microprogram contains instructions capable of controlling the arithmetic unit, the multiplier, the shift register, and the waveform memory depending upon a particular configuration.

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patent: 3812470 (1974-04-01), Murtha et al.
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patent: 4090250 (1978-05-01), Carlson et al.
patent: 4144582 (1979-05-01), Hyatt
patent: 4146931 (1979-03-01), Delforge
patent: 4393468 (1983-07-01), New
Arnold, R. G. et al., The Architecture of the MMBC System, Journal of Digital Systems, vol. V, No. 1/2, 1981, pp. 39-65.
Vick, C. R. et al., Pepe Architecture--Present and Future, Proceedings of the National Computer Conference, Jun. 5-8, 1978, pp. 981-992.

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