Digital read channel utilizing analog-to-digital converter with

Details Digital read channel utilizing analog-to-digital converter with Digital read channel utilizing analog-to-digital converter with

1995-03-07

1997-06-03

Gaffin, Jeffrey A.

Coded data generation or conversion

Converter compensation

341155, 360 66, G11B 5003, G11B 500

Patent

active

056359349

ABSTRACT:
An analog-to-digital converter (ADC) voltage offset (VOS) reduction circuit architecture is for use with an ADC that includes a resistive ladder network and a differential-to-single ended converter. The DC level of the single-ended output of the differential-to-single ended converter is nominally set at the mid-point of the resistive ladder network. The VOS reduction circuit includes a VOS comparator bank that receives the single-ended output, compares it with a plurality of input signals from the resistive ladder network, and provides the result of the comparison as a plurality of VOS comparator bank signals. A current digital-to-analog converter (IDAC) is coupled to receive the VOS comparator bank signals, via a latch bank, and to provide a current responsive thereto. The current from the IDAC may be provided as a trim current for adjusting the DC level of the single-ended output of the ADC differential-to-single ended converter to be closer to the mid-point of the resistive ladder network, thus reducing voltage offset caused, for example, by variations in process and temperature.

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