Digital quadrature detection circuit

Details Digital quadrature detection circuit Digital quadrature detection circuit

1997-05-13

1999-10-26

Pham, Chi H.

Pulse or digital communications

Receivers

Particular pulse demodulator or detector

375280, 375332, H03D 100

Patent

active

059740965

ABSTRACT:
An object is to provide a digital quadrature detection circuit wherein, without making the circuit complicated and without lowering performance, the operating frequency can be lowered and power consumption can be reduced. There are provided: a quasi-synchronous detector that takes the exclusive logical sum of a binary-converted intermediate frequency signal and a carrier signal, sampling means that respectively sample the output of the quasi-synchronous detector at M phases (where M is an integer of 1 or more) for each symbol, a bit adder that generates an M-bit parallel signal from the output signals of these, and low-pass filters that extract the low frequency components from this output. Whereas conventionally a 100-times clock pulse was employed in order to obtain an M-bit parallel signal, in this case, a 20-times clock pulse is sufficient, due to the provision of five sampling means.

REFERENCES:
patent: 5241567 (1993-08-01), Shimakata
patent: 5313170 (1994-05-01), Kojima
patent: 5406218 (1995-04-01), Ishihara et al.
patent: 5426669 (1995-06-01), Yamamoto et al.
patent: 5574399 (1996-11-01), Oura et al.
patent: 5578947 (1996-11-01), Kojima

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