Digital quadrature demodulation and decimation without...

Details Digital quadrature demodulation and decimation without... Digital quadrature demodulation and decimation without...

2005-01-04

2005-01-04

Ha, Dac V. (Department: 2634)

Pulse or digital communications

Receivers

Angle modulation

C375S340000, C329S305000, C329S310000, C329S364000

Reexamination Certificate

active

06839389

ABSTRACT:
One embodiment of the present invention includes a gating circuit, a demultiplexer, and an integrator. The gating circuit gates an input sample with a first clock, the input sample being clocked by a sampling clock N times faster than the first clock. The demultiplexer demultiplexes the gated input sample to generate in-phase and quadrature samples. The integrator integrates the in-phase and quadrature samples to generate in-phase and quadrature decimated samples corresponding to the in-phase and quadrature samples, respectively. Each of the in-phase and quadrature decimated samples having K bits.

REFERENCES:
patent: 5422909 (1995-06-01), Love et al.
patent: 5881107 (1999-03-01), Termerinac et al.
patent: 6282248 (2001-08-01), Farrow et al.

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