Digital QAM modulator using post filtering carrier recombination

Details Digital QAM modulator using post filtering carrier recombination Digital QAM modulator using post filtering carrier recombination

1998-03-19

2000-10-31

Chin, Stephen

Pulse or digital communications

Systems using alternating or pulsating current

Plural channels for transmission of a single pulse train

375298, 375277, 375308, 375332, H04L 702

Patent

active

061413879

ABSTRACT:
The efficient quadrature amplitude modulator of the present invention allows from 6 to 8 independent compressed channels to occupy a 6 MHz bandwidth while reducing processing power by 33 percent for 8 levels of modulation offered by 64-QAM and by 25 percent for 16 levels of modulation offered by 256-QAM. The modulator achieves this efficiency using an improved digital filter architecture combining the modulation and filtering with post filtering carrier combination. The QAM modulator presented is implemented with a reduction in the total number of binary parallel multipliers. To increase operational throughput, the speed of operation increases with the use of LUTs (look-up tables) storing precomputed filter weighting coefficients. The reduction in multipliers is also achieved by using post filtering carrier combination which similarly reduces the number of MAC operations performed during filtering. The invention can be construction either as a FPGA (field programmable gate array) or an ASIC (application specific integrated circuit).

REFERENCES:
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patent: 5787133 (1998-07-01), Marchetto et al.
patent: 5825829 (1998-10-01), Borazjani et al.
H. Samueli/B. Wong, A VLSI Architecture for a High-Speed All-Digital Quadrature Modulator and Demodulator for Digital Radio Applications, IEEE Journal on Selected Areas in Communications, vol. 8, No. 8, 1512-1519 (Oct. 1990).

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