Digital push-pull driver circuit

Details Digital push-pull driver circuit Digital push-pull driver circuit

1990-01-16

1992-06-30

Zazworsky, John

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307263, 307268, 307579, H03K 512

Patent

active

051265885

ABSTRACT:
A digital push-pull driver circuit comprising two output transistors which are alternatingly controlled into the conducting state by a data control circuit and to whose common connection point a load to be driven is connected. One slope steepness reducing, enable-dependent delay circuit each is connected between the control electrode of each of the two output transistors and the data control circuit. The output of each delay circuit is connected to an enable input of the respective other delay circuit. The delay times of the two delay members are at least as long as the width of the steepness-reduced pulse slopes in terms of time.

REFERENCES:
patent: 3845328 (1974-10-01), Hollingsworth
patent: 3906255 (1975-09-01), Mensch, Jr.
patent: 3961269 (1976-11-01), Alvarez, Jr.
patent: 4164842 (1979-07-01), Ebihara
patent: 4540904 (1985-04-01), Ennis
patent: 4622482 (1986-11-01), Ganger
patent: 4725747 (1988-02-01), Stein et al.
patent: 4843595 (1989-06-01), Suzuki

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