Digital pulse width modulator

Details Digital pulse width modulator Digital pulse width modulator

2006-01-24

2009-12-01

Kim, Kevin Y (Department: 2611)

Pulse or digital communications

Pulse width modulation

Reexamination Certificate

active

07627032

ABSTRACT:
A DPWM (1) has a delay lock loop (4) which receives an input clock signal and provides an out-of-phase delayed clock at the output of each of eight delay cells (35). A multiplexer (5) selects one of the delay cell outputs at any one time. This allows the DPWM (1) to have eight times the resolution which would otherwise be achieved with the same input clock. A programmable module (2) has a control block (20) which interfaces with external CPU and DSP hosts and transmits programmed parameters to finite state machine controllers (15), each providing an independent output.

REFERENCES:
patent: 5594631 (1997-01-01), Katoozi et al.
patent: 5602464 (1997-02-01), Linkowsky et al.
patent: 6038265 (2000-03-01), Pan et al.
patent: 6538523 (2003-03-01), Sugita et al.
patent: WO03/005779 (2003-01-01), None
patent: WO03/050637 (2003-06-01), None
Dancy et al, IEEE Trans . . . , vol. 8, No. 3, Jun. 2000, pp. 1-12, High-Efficiency Multiple-Output DC-DC Conversion for Low- . . . .

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