Digital programmable delay element

Details Digital programmable delay element Digital programmable delay element

2000-05-01

2001-07-03

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S271000, C327S281000

Reexamination Certificate

active

06255879

ABSTRACT:

FIELD OF INVENTION
This invention relates to delay lines and more particularly to programmable delay lines.
BACKGROUND OF INVENTION
As manufacturing of an integrated circuit becomes highly dense with numerous parasitic effects, it is increasingly difficult to determine a chip behavior from simulation. Build-in delay elements are used in a VLSI chip as a viable alternative for adjusting timing discrepancies.
FIG. 1A
schematically shows a typical circuit of a delay element according to the prior art. Transfer devices D1
101
, D2
102
, D3
103
, D4
104
each have a controlled current path from the delay line
110
through a serially connected fixed value capacitor, C
105
, 2C
106
, 4C
107
or 8C
108
, to ground respectively. In operation, when a transfer device is selectively turned on, current flows from the input line through the transfer device and then through the serially connected fixed value capacitor to ground. The resistive load (R
L
) present on the delay line in conjunction with the capacitance of the fixed capacitor form an RC circuit having a time constant (T) equal to T=R
L
*C. By turning on more than one transfer device, parallel capacitance is added thereby increasing the time constant.
The delay of the signal present on the delay line is increased as more parallel capacitance is added. This function is graphically shown in
FIG. 1B
where the rise time of the signal propagating through the delay line increases as capacitance is increased. A conventional solution does not allow for altering the delay in fix time intervals due to changing nature of a transistor's resistance. Accordingly, it is desirable to provide a programmable delay element that can provide a delay with many available delay combinations.
SUMMARY OF INVENTION
The invention is to provide a programmable delay element that can produce a variable delay with many different delay combinations. The invention creates a variable delay through logic gates. A plurality of transmission gates are used to transfer a signal through a plurality of fixed delay lines. Four parallel coupled signal paths, each path having a fixed delay, form the basis of the invention. By selecting a path or by serially adding successive paths, the desired delay of the signal present on the delay line can be achieved.


REFERENCES:
patent: 5365204 (1994-11-01), Angiulli et al.
patent: 6163194 (2000-12-01), Truong et al.

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