Patent
1993-04-13
1995-04-25
Lall, Parshotam S.
G06F 930
Patent
active
054106591
ABSTRACT:
A digital processor has a data processing unit having arithmetic/logic operation circuits, an instruction memory for storing an instruction word, and an instruction decoder for decoding the instruction word read from the instruction memory and outputting the control signals respectively to the arithmetic/logic operation circuits. Each instruction word has at least a first control field and a second control field. The instruction decoder has two decoding circuits. Each of the decoding circuits corresponds to each group of the arithmetic/logic operation circuits, receives the instruction word for decoding the second control field into a control signal and outputs an ENABLE signal. The ENABLE signal from the first decoding circuit is applied to the second decoding circuit, and the ENABLE signal from the second decoding circuit is applied to the first decoding circuit. Only one of the first and second decoding circuits outputs a control signal at a time.
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Patterson et al. "Computer Architecture-A Quantitative Approach" (1990) p. 208.
Lall Parshotam S.
NEC Corporation
Vu Viet
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