Digital processor with floating point multiplier and adder suita

Details Digital processor with floating point multiplier and adder suita Digital processor with floating point multiplier and adder suita

1981-10-15

1985-04-16

Malzahn, David H.

Boots, shoes, and leggings

G06F 748

Patent

active

045119902

ABSTRACT:
A signal processor having a wide dynamic range and which can process both data in the fixed point representation and data in the floating point representation by the use of a single floating-point arithmetic circuit is capable of processing digital signals, such as voice signals, at high speed and in real time. In addition, this signal processor is capable of executing data input/output operations with an external circuit in the data format of the fixed point representation and of performing internal operations in the floating point representation format. Further, conversion of an operational result from fixed point representation to floating point representation, and vice versa, can be performed internally in accordance with program instruction.

REFERENCES:
patent: 3551665 (1970-12-01), Powers et al.
patent: 3697734 (1972-10-01), Booth et al.
patent: 3871578 (1975-03-01), Van De Goor et al.
patent: 4075704 (1978-02-01), O'Leary
patent: 4130879 (1978-12-01), Cushing
patent: 4217657 (1980-08-01), Handly et al.
patent: 4229801 (1980-10-01), Whipple

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