Boots – shoes – and leggings
Patent
1990-05-31
1993-09-21
Fleming, Michael R.
Boots, shoes, and leggings
395550, 364DIG1, 3642434, 3642514, 364260, 3642601, 3642602, 3642702, 3642709, 3642715, G06F 1300
Patent
active
052476367
ABSTRACT:
A clock circuit (12) normally couples clock pulses to a microprocessor (11), which is capable of accessing memory devices (13,14) having different access times. Access of a "slow" memory device 14 is detected by the clock circuit, and in response thereto, one or more clock pulses are not coupled to the microprocessor. This suspends operation of the microprocessor for a suitable amount of time so that the microprocessor reads valid data from the slow memory device. The number of clock pulses blocked from reaching the microprocessor can be set in a delay circuit (28) in the clock circuit.
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Patent Abstracts of Japan, vol. 13, No. 149 (P-855) (3497) 12 Apr. 1989 & JP-A-63 311 533 (Mitsubishi Electric Corp.) 20 Dec. 1989 *abstract*.
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Minnick Jeffrey A.
Spina Warren J.
Fleming Michael R.
International Business Machines - Corporation
McArdle J. J.
Sheikh Ayaz R.
Steinberg W. H.
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